Technique for Minimizing Power Consumption in Array Multipliers through Input Vector Ordering

Abstract

It is known that, excessive power dissipation can cause over heating, which reduces the life time of the chip and degrades the circuit performance. Local hot spots occur due to large instantaneous power dissipation. We propose a methodology based on reordering the input vectors to reduce the power dissipated in combinational circuits. Experimental results indicate that the proposed technique achieves reduction in average power, reduction in peak power and reduction in difference between maximum and minimum instantaneous power. In this paper, the results obtained by applying this technique to a specific circuit, an array multiplier are reported. As array multipliers are extensively used in digital signal processing (DSP) applications, we feel that this technique will have far-reaching implications in the design of low power processors