On-chip analog response extraction with 1-bit /spl Sigma/-/spl Delta/ modulators

Hao-Chiao Hong, Jiun-Lang Huang, K. Cheng, Cheng-Wen Wu
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引用次数: 9

Abstract

Because of their relative robustness to process variation, /spl Sigma/-/spl Delta/ modulation techniques are particularly suitable for VLSI implementations. In this paper, we propose to employ the 1-bit /spl Sigma/-/spl Delta/ modulation ADC (analog-to-digital converter) as the on-chip analog response extractor for analog/mixed-signal BIST (built-in self-test) applications. To validate the idea, a prototype chip with the proposed BIST circuitry has been designed and fabricated. Performance of the BIST circuitry is validated (up to 87 dB dynamic range), and measurement results of the circuit under test (CUT), a 2nd-order low-pass filter, are presented.
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片上模拟响应提取与1位/spl Sigma/-/spl Delta/调制器
由于对工艺变化具有相对的鲁棒性,/spl Sigma/-/spl Delta/调制技术特别适用于VLSI实现。在本文中,我们建议采用1位/spl Sigma/-/spl Delta/调制ADC(模数转换器)作为片上模拟响应提取器,用于模拟/混合信号BIST(内置自检)应用。为了验证这个想法,已经设计并制造了一个带有所提出的BIST电路的原型芯片。验证了BIST电路的性能(动态范围高达87 dB),并给出了被测电路(CUT)的测量结果,该电路是一个二阶低通滤波器。
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