{"title":"A Domain Decomposition Method for the Finite Element Simulation of Circuit Board Interconnects","authors":"Kaiyu Mao, Jilin Tan, Jianming Jin","doi":"10.1109/EPEP.2007.4387181","DOIUrl":null,"url":null,"abstract":"A domain decomposition method (DDM) is developed to improve the efficiency of the finite element simulation of interconnects on multilayered printed circuit boards, which helps reduce memory requirements and CPU time without sacrificing the final accuracy. It takes advantage of the multilayered structure and decomposes the board into several single layers separated by power or ground planes. The simulation of each layer can be carried out independently. Connections between neighboring layers are realized by small holes (\"vias\"), whose computation is accomplished in a trivial final combination procedure. The total memory requirement is only related to the largest single layer. The CPU time is also found to be less than that of the full board simulation. This domain decomposition method further permits a convenient and practical way for parallel computation.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Electrical Performance of Electronic Packaging","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPEP.2007.4387181","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A domain decomposition method (DDM) is developed to improve the efficiency of the finite element simulation of interconnects on multilayered printed circuit boards, which helps reduce memory requirements and CPU time without sacrificing the final accuracy. It takes advantage of the multilayered structure and decomposes the board into several single layers separated by power or ground planes. The simulation of each layer can be carried out independently. Connections between neighboring layers are realized by small holes ("vias"), whose computation is accomplished in a trivial final combination procedure. The total memory requirement is only related to the largest single layer. The CPU time is also found to be less than that of the full board simulation. This domain decomposition method further permits a convenient and practical way for parallel computation.
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