Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387180
E. Liu, Xingchang Wei, Z. Oo, E. Li, Lewei Li
A system-level modeling approach, which combines the MoM (method of moments) and the SMM (scattering matrix method) has been presented for the modeling of advanced electronic packages (Oo et al., 2007). The focus of this paper is on addressing the problems of multilayered multiple via coupling and finite ground effects by the SMM method. Significant extensions of the SMM method facilitate the modeling of coupling among densely populated vias in multilayered packages with finite power/ground planes. The proposed approach is suitable for the signal and power integrity, and even EMI analysis of packages at system level.
提出了一种系统级建模方法，该方法结合了矩量法(MoM)和散射矩阵法(SMM)，用于高级电子封装的建模(Oo et al.， 2007)。本文的重点是用SMM方法解决多层多通孔耦合和有限地面效应问题。SMM方法的重要扩展有助于对具有有限功率/地平面的多层封装中密集过孔之间的耦合进行建模。该方法适用于系统级封装的信号和功率完整性分析，甚至电磁干扰分析。
{"title":"Modeling of Advanced Multilayered Packages with Multiple Vias and Finite Ground Planes","authors":"E. Liu, Xingchang Wei, Z. Oo, E. Li, Lewei Li","doi":"10.1109/EPEP.2007.4387180","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387180","url":null,"abstract":"A system-level modeling approach, which combines the MoM (method of moments) and the SMM (scattering matrix method) has been presented for the modeling of advanced electronic packages (Oo et al., 2007). The focus of this paper is on addressing the problems of multilayered multiple via coupling and finite ground effects by the SMM method. Significant extensions of the SMM method facilitate the modeling of coupling among densely populated vias in multilayered packages with finite power/ground planes. The proposed approach is suitable for the signal and power integrity, and even EMI analysis of packages at system level.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115197157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387125
V. Kollia, A. Cangellaris
This paper presents an extended version of the segmentation procedure for planar circuit analysis to the electromagnetic modeling of the power distribution network of packages and boards with multiple power and ground planes.
{"title":"Extended Segmentation Procedure for Electromagnetic Modeling of the Power Distribution Network","authors":"V. Kollia, A. Cangellaris","doi":"10.1109/EPEP.2007.4387125","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387125","url":null,"abstract":"This paper presents an extended version of the segmentation procedure for planar circuit analysis to the electromagnetic modeling of the power distribution network of packages and boards with multiple power and ground planes.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123632189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387113
N. Singh, B. Mutnury, C. Wesley, N. Pham, E. Matoglu, M. Cases, D. de Araujo
Today's high speed electrical systems exhibit ever increasing complexity generation after generation. This increased complexity results in additional design parameters which the system designer must choose carefully to obtain the optimum design. Often, the number of these design variables is large enough that a brute-force search of the design space is not feasible. Statistical techniques like design of experiments (DoE) cannot accurately find the best and worst case corners. This paper introduces the concept of swarm intelligence for the first time for electrical design space exploration. Specifically, the discrete particle swarm optimization (PSO) is used to arrive at an optimum combination of design parameters for various electrical interfaces. The PSO algorithm is shown to have great potential as a robust and efficient alternative to statistical techniques currently used in high speed electrical design optimization.
{"title":"Swarm Intelligence for Electrical Design Space Exploration","authors":"N. Singh, B. Mutnury, C. Wesley, N. Pham, E. Matoglu, M. Cases, D. de Araujo","doi":"10.1109/EPEP.2007.4387113","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387113","url":null,"abstract":"Today's high speed electrical systems exhibit ever increasing complexity generation after generation. This increased complexity results in additional design parameters which the system designer must choose carefully to obtain the optimum design. Often, the number of these design variables is large enough that a brute-force search of the design space is not feasible. Statistical techniques like design of experiments (DoE) cannot accurately find the best and worst case corners. This paper introduces the concept of swarm intelligence for the first time for electrical design space exploration. Specifically, the discrete particle swarm optimization (PSO) is used to arrive at an optimum combination of design parameters for various electrical interfaces. The PSO algorithm is shown to have great potential as a robust and efficient alternative to statistical techniques currently used in high speed electrical design optimization.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114350777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387144
Jihong Ren, D. Oh
Signal integrity issues such as inter-symbol interference (ISI) limit the maximum data rates achievable on off-chip interconnect. Sophisticated equalization techniques must be used to mitigate the impact of ISI in order to achieve multi-gigahertz data rates. Conventional methods minimize ISI either at the data sampling time (Stojanovic, 2006) for better signal to interference ratio (SIR) or at the edge sampling time (Brunn, 2005) for smaller data-dependent deterministic jitter (DDJ). However, common in high-speed I/O specifications is the received eye mask which specifies the minimum received opening of a data eye both in voltage and time. This paper presents multiphase equalization that effectively trades off voltage and timing margin for a given eye mask specification. We use the statistical link performance analysis framework in (Oh, 2007) to show the effectiveness and flexibility of the methods in controlling eye shape and trading off timing and voltage margins. Regression data over 13 backplane channels show that compared with traditional ZFE methods, multiphase equalization provide better overall link performance.
{"title":"System Margin Improvement with Multiphase Equalization for High-Speed Links","authors":"Jihong Ren, D. Oh","doi":"10.1109/EPEP.2007.4387144","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387144","url":null,"abstract":"Signal integrity issues such as inter-symbol interference (ISI) limit the maximum data rates achievable on off-chip interconnect. Sophisticated equalization techniques must be used to mitigate the impact of ISI in order to achieve multi-gigahertz data rates. Conventional methods minimize ISI either at the data sampling time (Stojanovic, 2006) for better signal to interference ratio (SIR) or at the edge sampling time (Brunn, 2005) for smaller data-dependent deterministic jitter (DDJ). However, common in high-speed I/O specifications is the received eye mask which specifies the minimum received opening of a data eye both in voltage and time. This paper presents multiphase equalization that effectively trades off voltage and timing margin for a given eye mask specification. We use the statistical link performance analysis framework in (Oh, 2007) to show the effectiveness and flexibility of the methods in controlling eye shape and trading off timing and voltage margins. Regression data over 13 backplane channels show that compared with traditional ZFE methods, multiphase equalization provide better overall link performance.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125639222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387175
B. Buhrow, E. Daniel, B. Gilbert
Output driver models play a critical role in simultaneous switching noise (SSN) analysis. However, their accuracy must often be compromised with simplicity of implementation for large scale SSN simulations. We present an approach for creating simple, fast, and accurate macromodels of output drivers. To demonstrate their usefulness, simulation results in multi-IO SSN simulations are shown and compared to those obtained from transistor level SPICE libraries.
{"title":"A New Macromodeling Approach for Digital Output Drivers and Application in Simultaneous Switching Noise Analysis","authors":"B. Buhrow, E. Daniel, B. Gilbert","doi":"10.1109/EPEP.2007.4387175","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387175","url":null,"abstract":"Output driver models play a critical role in simultaneous switching noise (SSN) analysis. However, their accuracy must often be compromised with simplicity of implementation for large scale SSN simulations. We present an approach for creating simple, fast, and accurate macromodels of output drivers. To demonstrate their usefulness, simulation results in multi-IO SSN simulations are shown and compared to those obtained from transistor level SPICE libraries.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"106 4 Suppl 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130455461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387196
A. Hesford, J. Morsey, W. Chew, A. Deutsch, H.H. Smith
A parallel LU decomposition algorithm is presented to take advantage of the sparse impedance matrix produced by the reduced-coupling method. This algorithm allows rapid simulation of very large chip and packaging problems. A representative example is shown for a wide, on-chip data-bus that required one million surface unknowns and the computational power of a 1024-node IBM BlueGene cluster with distributed memory.
{"title":"Parallelization of the Reduced-Coupling Technique for a Method-of-Moments-Based Field Solver Used for Product-Level Wide Data-Bus Analysis","authors":"A. Hesford, J. Morsey, W. Chew, A. Deutsch, H.H. Smith","doi":"10.1109/EPEP.2007.4387196","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387196","url":null,"abstract":"A parallel LU decomposition algorithm is presented to take advantage of the sparse impedance matrix produced by the reduced-coupling method. This algorithm allows rapid simulation of very large chip and packaging problems. A representative example is shown for a wide, on-chip data-bus that required one million surface unknowns and the computational power of a 1024-node IBM BlueGene cluster with distributed memory.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133873668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387143
Chris Madden, Sam Chang, D. Oh, C. Yuan
Jitter Amplification is a real concern in the design of PCB clock channels if the frequency of the clock is high and the PCB trace is relatively long. In this paper, we confirm the earlier finding of clock channel jitter amplification [1], using a multiple edge response (MER) simulation method instead of jitter impulse response for the channel. However, we show that both white Random Jitter (wRJ) and Sinusoidal Jitter (SJ) amplification are a function of the signal loss in the channel, and as such, are reduced significantly with equalization. Furthermore, simulated CMOS Tx RJ, which is dominated by its low frequency components, is amplified less than is wRJ, even for channels with >20dB signal loss. Measurement results are correlated with simulations for 2-6 GHz clocks on a channel containing 24-inches of PCB trace.
{"title":"Jitter Amplification Considerations for PCB Clock Channel Design","authors":"Chris Madden, Sam Chang, D. Oh, C. Yuan","doi":"10.1109/EPEP.2007.4387143","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387143","url":null,"abstract":"Jitter Amplification is a real concern in the design of PCB clock channels if the frequency of the clock is high and the PCB trace is relatively long. In this paper, we confirm the earlier finding of clock channel jitter amplification [1], using a multiple edge response (MER) simulation method instead of jitter impulse response for the channel. However, we show that both white Random Jitter (wRJ) and Sinusoidal Jitter (SJ) amplification are a function of the signal loss in the channel, and as such, are reduced significantly with equalization. Furthermore, simulated CMOS Tx RJ, which is dominated by its low frequency components, is amplified less than is wRJ, even for channels with >20dB signal loss. Measurement results are correlated with simulations for 2-6 GHz clocks on a channel containing 24-inches of PCB trace.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127164827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387171
G. Antonini, J. Ekman, A.E. Ruehlis
Excessive compute time is becoming a key problem for high performance system modeling as the complexity of the electromagnetic and circuit models is increasing. At the same time the PEEC models are locally becoming more complex with the increased importance of dielectric and skin-effect losses. In this paper, we consider a combined approach where waveform relaxation is used for the predominant weak coupling while a Gaussian matrix solver is used for the parallelization of the strongly coupled parts of the EM/Ckt solver.
{"title":"Parallel Waveform Relaxation and Matrix Solution for Large PEEC Model Problems","authors":"G. Antonini, J. Ekman, A.E. Ruehlis","doi":"10.1109/EPEP.2007.4387171","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387171","url":null,"abstract":"Excessive compute time is becoming a key problem for high performance system modeling as the complexity of the electromagnetic and circuit models is increasing. At the same time the PEEC models are locally becoming more complex with the increased importance of dielectric and skin-effect losses. In this paper, we consider a combined approach where waveform relaxation is used for the predominant weak coupling while a Gaussian matrix solver is used for the parallelization of the strongly coupled parts of the EM/Ckt solver.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132978261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387178
T. Demeester, D. De Zutter
The Dirichlet to Neumann operator, already used to model inductive and resistive behaviour of transmission lines, is modified for application to capacitance calculations in lossy finite dielectrics. Some broadband results are presented to validate the new technique.
{"title":"Determination of the broadband transmission line parameters of iossy lines using the Dirichlet to Neumann operator","authors":"T. Demeester, D. De Zutter","doi":"10.1109/EPEP.2007.4387178","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387178","url":null,"abstract":"The Dirichlet to Neumann operator, already used to model inductive and resistive behaviour of transmission lines, is modified for application to capacitance calculations in lossy finite dielectrics. Some broadband results are presented to validate the new technique.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130927195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/EPEP.2007.4387167
Franklin Baez, Peter Van Dyke, Christopher Spring
We describe a methodology to route differential pairs in vertical layers in a high performance multi-chip module ceramic package. By matching the impedance of these vertical differential pairs to their conventional counterparts and adopting a power distribution topology that effectively isolates these pairs from noise aggressors, routing was improved by 17% and simultaneous switching noise decreased by 60%. The methods described in this paper were applied successfully in the design of an IBM ceramic multi-chip module (MCM) package with good electrical performance.
{"title":"Vertical Differential Pair Routing in High Performance Ceramic Multi-chip Module Packages","authors":"Franklin Baez, Peter Van Dyke, Christopher Spring","doi":"10.1109/EPEP.2007.4387167","DOIUrl":"https://doi.org/10.1109/EPEP.2007.4387167","url":null,"abstract":"We describe a methodology to route differential pairs in vertical layers in a high performance multi-chip module ceramic package. By matching the impedance of these vertical differential pairs to their conventional counterparts and adopting a power distribution topology that effectively isolates these pairs from noise aggressors, routing was improved by 17% and simultaneous switching noise decreased by 60%. The methods described in this paper were applied successfully in the design of an IBM ceramic multi-chip module (MCM) package with good electrical performance.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127960790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：