Testable design for BiCMOS stuck-open fault detection

Abstract

BiCMOS devices exhibit sequential behavior under transistor stuck-open (s-open) faults. In addition to the sequential behavior, delay faults are also present. Detection of s-open faults exhibiting sequential behavior need two or multipattern sequences, and delay faults are all the more difficult to detect. A new design for testability scheme is presented for single BJT BiCMOS logic gates which uses only two extra transistors to improve the circuit testability regardless of timing skews/delays, glitches or charge sharing among internal nodes. It requires only a single vector instead of the two or multipattern sequences. The testable design scheme presented also avoids the requirement of generating tests for delay faults.<>