Jack Yi Jie Ng, Kok Heng Lau, C. N. Liew, L.L. Goh, Chia-Li Song, Lee Kean Yong
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引用次数: 0
Abstract
This paper presents two case studies, which are based on 10nm Field Programmable Logic Array (FPGA) technology, to highlight the approach of defect localization for scan Automated Test Pattern Generation (ATPG) failure through additional layout aware analysis, and the combination of layout study, photon emission analysis (PEM), parallel lapping, nanoprobing and Scanning Emission Microscope (SEM) inspection.
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