Warpage measurement of substrates and printed circuit boards with Shadow Moiré

Abstract

Warpage of ball grid array substrate and printed circuit board is a common issue during reflow process due to the mismatch of coefficients of thermal expansion. With the development of the substrate becoming larger and larger, there is a higher risk of reflow defects caused by warpage. In this paper, an open soldering failure, head-in-pillow, caused by warpage is reported when ball grid array package was reflowed onto printed circuit board. Shadow moiré technique was then used for dynamic warpage analysis on both sides of ball grid array substrate and printed circuit board. The dynamic warpage measurement results indicate that Al corner is the highest risk location for head-in-pillow failure, which matches that of actual head-in-pillow defect location very well. Design of experiment on reflow profile and stencil aperture design were conducted. Based on design of experiment results and considering the reflow process control window, medium temperature profile (U1 peak temperature of 240°C) with aperture design of the stencil 2 was chosen for manufacturing.