A New Semiconductor Package Design Flow and Platform Applied on High Density Fan-out Chip

Abstract

In recent years, because the needs of 5G mobile communications, artificial intelligence, self-driving cars, and high-speed networks product are highly increasing, more and more IC design companies have invested in a lots of computing and high-performance computing device development. At present, the package type used in such high-performance computing product mass production is 2.5D IC package with ultra-high density I/O, which is special for packaging of IC products such as AI, high performance GPU, and high-speed networking devices. Compared to the traditional Flip Chip BGA (FCBGA) package on the market, the 2.5D package has a unique silicon interposer, and there are ASIC chip and HBM chips on the silicon interposer. Between the ASIC chip and the HBM chips, a lot of high-speed signal lines and thousands of small vias are connected. In addition to the signal line between the ASIC chip and the HBM chip, the silicon interposer has an important structure-TSV (Through Silicon Via) to act as the connection between the ASIC chips or the HBM chips and the package substrate. Because of the existing of TSV, the production yield of the silicon interposer is not easy to increase. Considering productivity and cost, some OSAT (Outsourced Semiconductor Assembly and Test) companies hence [1]–[5] proposed some TSV-free packaging structures, such as FOCoS (Fan-out Chip on Substrate). According to different process, there are Chip First FOCoS and Chip last FOCoS, which are suitable for different applications and production costs [6]. The research and discussion in this paper, there are package design with the structure of FOCoS for an actual high-performance computing IC device with two ASIC chips. In the process of this actual project, the SiP-id (System-in-Package Intelligent Design) design platform was used to complete the routings of ultra-high density I/O such as the Si interposer MEOL (Middle End of Line) and Fan-Out RDL. Compared with the traditional design platform, it was greatly pull-in design cycle time. The design time and the accuracy of the design are improved obviously. In addition, this paper also delivers a lot of self-developed programs to link the design and validation tools from different vendors.