The Evaluation of Error Detection Probability at the Outputs of Combinational Circuits Under Concurrent Error Detection on the Basis of Summation Codes

Abstract

One of the most common approaches to building concurrent error detection systems of combinational logical circuits is the application of separable block-structured codes. In previous studies of the authors it was established that characteristics of the code directly determine properties of the concurrent error detection system on detecting errors in the unit under test. The choice of a code influences the method of implementation of the concurrent error detection system, including the solution of tasks aimed at control organization of the device which detects all types of errors from the given class, or errors of the given class with the predetermined probability. The authors of the study in question offer the evaluation procedure of error-detection probability in combinational logical circuits under concurrent error detection of the latter on the basis of separable block-structured codes. The authors only consider the model of single stuck-at faults at the outputs of logical elements of the inner structure of a combinational circuit, however the approach itself is universal and after certain improvement may be applied for the evaluation of error-detection probability at the outputs of combinational circuits taking into account other fault models. The example of calculating errordetection probability was given, as well as test results of check combinational circuits from LGSynth'89 set on the evaluation of error-detection probability at the outputs of circuits under concurrent error detection, on the basis of the weight-based code with summation without carries.