Ultra low power 2-tier 3D stacked sub-threshold H.264 intra frame encoder

Abstract

Digital circuits used in sensor networks require longer battery life and do not demand a fast frequency of operation. Sub-threshold circuits for such applications are an attractive option. Three dimensional ICs (3DICs) on the other hand is an emerging technology which helps in miniaturization and reduction in interconnects, resulting in power saving and performance improvement. Several works on sub-threshold circuits and TSV based 3DICs have been studied independently but none have studied the impact of 3D stacking of sub-threshold circuits. We design and study an ultra-low power 2-tier 3D sub-threshold implementation of H.264 intra frame encoder that encodes video frames. The encoder consumes 0.73μW power at 16.13 KHz clock frequency for a typical application of encoding a Common Image Format (CIF) frame. The motivation is to assess the feasibility of the use of extreme low power video encoders in image sensor based sensor networks. Low power operation is highly beneficial to such unattended sensor networks by extending their battery life. Sub-threshold design helps us in this respect while 3D stacking minimizes footprint area, helps in off-chip to on-chip memory integration and improves timing performance.