Reinforcement Learning Enabled Throughput Optimization for Interconnection Networks of Interposer-based system

Abstract

Silicon interposer enables 2.5D stacking of memory chips and processor chips to pursue advanced memory access performance. In interposer-based system, different traffic transfers through network-on-interposer (NoI) lays on the silicon interposer which makes NoI throughput important to transmit the mass of data. However, the performance of the existing topology varies under different traffic patterns. In this paper, we use reinforcement learning (RL) is adapted to further optimize the throughput of NoI in various traffic. We design a dedicated RL framework for NoI enviroment to enable performance improvement. Three algorithms are used to maximize the throughput as well as reward in the RL Model. Simulation results demonstrate that the proposed RL approach provide higher throughput both in memory traffic and coherence traffic.