{"title":"An OBDD-representation of statecharts","authors":"J. Helbig, Peter Kelb","doi":"10.1109/EDTC.1994.326884","DOIUrl":null,"url":null,"abstract":"We present an effective method to translate a statechart into an ordered binary decision diagram (OBDD) representation of its transition system. By that it becomes possible to verify a system specified by a statechart by symbolic model checking, one of the most advanced automatic verification techniques. The method exploits the hierarchy in the relevance of information as is implied by the state structure and admits some redundancy to keep the \"decoding effort\" of each OBDD small. The method is implemented in the ESPRIT project FORMAT, where OBDD based transition systems serve as a common ground to verify specifications in VHDL or (a variant of) statecharts against temporal logic, symbolic timing diagrams, and each other.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"29","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDTC.1994.326884","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 29
Abstract
We present an effective method to translate a statechart into an ordered binary decision diagram (OBDD) representation of its transition system. By that it becomes possible to verify a system specified by a statechart by symbolic model checking, one of the most advanced automatic verification techniques. The method exploits the hierarchy in the relevance of information as is implied by the state structure and admits some redundancy to keep the "decoding effort" of each OBDD small. The method is implemented in the ESPRIT project FORMAT, where OBDD based transition systems serve as a common ground to verify specifications in VHDL or (a variant of) statecharts against temporal logic, symbolic timing diagrams, and each other.<>