Studying the Impact of Compound Semiconductor Material in Drain Region Extended Tunnel Transistor for SoC Applications

Upasana, Hasti Kasundra, Mridula Gupta, M. Saxena
{"title":"Studying the Impact of Compound Semiconductor Material in Drain Region Extended Tunnel Transistor for SoC Applications","authors":"Upasana, Hasti Kasundra, Mridula Gupta, M. Saxena","doi":"10.1109/EDKCON.2018.8770392","DOIUrl":null,"url":null,"abstract":"This work describes how conventional SOI-LDMOS has been converted into Drain Region Extended (DRE) Tunnel Transistor kind of structure by studying effects of various parameters that affects the device characteristics and modifying the device accordingly. Material-based study has been done in order to improvise the device functioning for System on Chip (SoC) applications in terms of higher breakdown and lower on-resistance.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDKCON.2018.8770392","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

This work describes how conventional SOI-LDMOS has been converted into Drain Region Extended (DRE) Tunnel Transistor kind of structure by studying effects of various parameters that affects the device characteristics and modifying the device accordingly. Material-based study has been done in order to improvise the device functioning for System on Chip (SoC) applications in terms of higher breakdown and lower on-resistance.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
研究复合半导体材料对SoC中漏极区扩展隧道晶体管的影响
本工作通过研究影响器件特性的各种参数的影响,并对器件进行相应的修改,描述了传统的SOI-LDMOS如何转化为漏极区扩展(DRE)隧道晶体管结构。基于材料的研究已经完成,以便在更高的击穿和更低的导通电阻方面为片上系统(SoC)应用即兴发挥器件功能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Stability Performance Comparison of a MTJ Memory Device Using Low-Dimensional HfO2, A12O3, La2O3 and h-BN as Composite Dielectric Stress Tuning in NanoScale FinFETs at 7nm Modeling Short Channel Behavior of Proposed Work Function Engineered High-k Gate Stack DG MOSFET with Vertical Gaussian Doping Study of Ag Doped SnO2 Film and its Response Towards Aromatic Compounds Present in Tea Stress Analysis in Uniaxially Strained-SiGe Channel FinFETs at 7N Technology Node
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1