Thin low-temperature gate oxides for vertical field-effect transistors

Abstract

We have investigated a novel technique for growing silicon dioxide gate dielectrics of 3-4 nm thickness using wet oxidation at a low temperature of 600/spl deg/C. While this method is ideally suited to prevent dopant diffusion in small vertical MOSFETs the quality of the oxide layers is comparable with conventional gate oxide layers being grown by rapid thermal processing. Ellipsometric thickness measurements show a thickness variation of only 2% over a 3" wafer. To determine the interface state density we used both the QS-HF-CV and the conductance measurement method. A comparison of these two measurement methods shows that the latter can be applied even in the presence of a high tunnelling cut-rent through the thin oxide layers. We were able to achieve a midgap interface state density of 3/spl times/10/sup 11/cm/sup -2/eV/sup -1/, being comparable with previously published results.