Gate stack process optimization for TDDB improvement in 28nm high-k/metal gate nMOSFETs

Abstract

The effects of IL (interfacial layer) thickness and nitrogen concentration of high-k layer on TDDB are comprehensively investigated for HK/MG nMOSFETs. Comparison of the TDDB characteristics based on IL thickness splits manifests that thick IL device exhibits longer failure time and lower SILC augment due to reduction of IL tunneling rate of electron. However, the gate leakage current of thick IL device is aggravated by decrease of total physical oxide thickness even for the same EOT due mainly to thinner HK thickness. Since SILC behavior is attributed to the bulk transient charge trapping by pre-existing defects in HK, the process optimization to reduce bulk defects in HK is a critical solution to improve TDDB in HK/MG nMOSFETs. In addition, nitridation process after HK deposition contributes to passivate oxygen vacancies in the gate dielectrics and removes electron leakage path driven by oxygen vacancies. Hence, nMOSFET with higher nitrogen concentration shows improved TDDB reliability without compromise in DC characteristics and the power law voltage acceleration factor.