Chein-Liang Chen, Chia-Hsing Lin, Hwan-Rei Lee, C. Jen
{"title":"A raster engine for computer graphics and image composition","authors":"Chein-Liang Chen, Chia-Hsing Lin, Hwan-Rei Lee, C. Jen","doi":"10.1109/APCCAS.1994.514532","DOIUrl":null,"url":null,"abstract":"A raster engine (RE) is designed and implemented to improve the performance of computer graphics and image composition. The RE hardware can release more than 50% CPU loads. Furthermore, if the approximated Phong method which is proposed is applied, 89% CPU operations are reduced by the RE. As the features of this design, the techniques including modified digital differential analyser (DDA), 2-level pipeline, and constant execution time for calculating cos/sup n/ /spl theta/ are proposed in RE. Three operation modes, Gouraud and Phong shading algorithm and image composition are incorporated in RE. This accelerator will be implemented by 0.8 um SPDM CMOS VLSI technology.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS.1994.514532","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A raster engine (RE) is designed and implemented to improve the performance of computer graphics and image composition. The RE hardware can release more than 50% CPU loads. Furthermore, if the approximated Phong method which is proposed is applied, 89% CPU operations are reduced by the RE. As the features of this design, the techniques including modified digital differential analyser (DDA), 2-level pipeline, and constant execution time for calculating cos/sup n/ /spl theta/ are proposed in RE. Three operation modes, Gouraud and Phong shading algorithm and image composition are incorporated in RE. This accelerator will be implemented by 0.8 um SPDM CMOS VLSI technology.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
