On-line error detectable carry-free adder design

Abstract

A technique for designing carry-free adders with on-line error checking capability is presented. The adders use signed binary digits (SBDs) internally. An adder consists of sign-magnitude binary to SBD converters, an intermediate adder block that generates partial sum and carry digits, a second adder block that produces a sum digit computed from a partial sum and a partial carry digit, and an error checker that indicates whether the code word corresponding to a final sum digit is error-free or not.