A Light-Weight Timing Resilient Scheme for Near-Threshold Efficient Digital ICs

Abstract

Near-threshold voltage (NTV) operation has potential to substantially improve the energy efficiency of digital integrated circuits (ICs). However, it also introduces excessive conservative timing margins. The timing resilient circuit was proved to be a promising solution to mitigate excessive timing margins. To realize more energy-efficient IC systems, the timing resilient circuits should be designed to be miniaturized and operate in wide-voltage-range (down to NTV).This paper develops a lightweight timing resilient scheme to enable the near-threshold efficient ICs. The proposed scheme based on our node transition signal detector (NTSD) design with merely 9 extra transistors. Combined with the data strobe Flip-Flops, the circuits are inserted into monitored points of the target ICs. To further reduce the overhead, we develop the mean-time-to-failure aware hybrid selection algorithm. Simulation results demonstrate that the proposed scheme enable the 40-nm CNN accelerator to work robustly at 0.38-1.1V with only 3.5% extra area overhead. Moreover, this scheme reduce area overhead by 54.68% and improve energy efficiency by 53.69% at 0.6V, compared with the presented Razor scheme. The advantage of our proposed method lies in that it consumes less extra overhead and can work stably in a wider voltage range.