Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301704
Yuka Nakamatsu, T. Kihara
The conventional direct radio frequency (RF) sampling receivers can not reduce their power consumption dynamically according to the power of input signals. The dynamic reduction enables them to decrease the total power consumption during operation to the level required for wireless terminals. We decrease the clock frequency of decimators in first-order recursive cascaded integrator-comb (CIC) filters after a time-interleaved ADC (TI-ADC) in a direct-RF sampling receiver, detecting higher power of input signals than the required sensitivity. Although the decimation slightly degrades the output signal-to-noise ratio (SNR) of the receiver, it reduces the power consumption of the digital building blocks. We design a 3.68-GS/s direct-RF sampling receiver, including analog and digital blocks, for Sub-GHz applications by using a 65-nm CMOS process. Simulations show that the receiver reduces a power consumption of 10.6 mW to 9.6 mW with a decimation factor of eight, whereas increasing the output SNR by 0.9 dB. This means that the receiver can decrease the power consumption, not degrading the output SNR, when receiving higher input power than the required level.
{"title":"Dynamic Reduction of Power Consumption in Direct-RF Sampling Receivers with Variable Decimation","authors":"Yuka Nakamatsu, T. Kihara","doi":"10.1109/APCCAS50809.2020.9301704","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301704","url":null,"abstract":"The conventional direct radio frequency (RF) sampling receivers can not reduce their power consumption dynamically according to the power of input signals. The dynamic reduction enables them to decrease the total power consumption during operation to the level required for wireless terminals. We decrease the clock frequency of decimators in first-order recursive cascaded integrator-comb (CIC) filters after a time-interleaved ADC (TI-ADC) in a direct-RF sampling receiver, detecting higher power of input signals than the required sensitivity. Although the decimation slightly degrades the output signal-to-noise ratio (SNR) of the receiver, it reduces the power consumption of the digital building blocks. We design a 3.68-GS/s direct-RF sampling receiver, including analog and digital blocks, for Sub-GHz applications by using a 65-nm CMOS process. Simulations show that the receiver reduces a power consumption of 10.6 mW to 9.6 mW with a decimation factor of eight, whereas increasing the output SNR by 0.9 dB. This means that the receiver can decrease the power consumption, not degrading the output SNR, when receiving higher input power than the required level.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127380976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301715
Ling Zhang, Weihong Zhou, Jingwei Li, Juan Li, Xin Lou
In this paper, the effects of normalization in the histogram of oriented gradients (HOG) are studied and a HOG feature extraction pipeline without normalization is proposed. In the proposed pipeline, the functionality of normalization is merged into the gradient generation step by replacing the original linear difference based gradients with logarithmic gradients. Due to the discrete property of the pixel values, the logarithmic operation can be easily implemented using a lookup table (LUT) with a depth of 2N, where N is the bit-width of the pixels. Theoretical analysis and experimental results show that the proposed normalization-free HOG feature based logarithmic gradient is close to the original version and can be used in the pedestrian detection algorithms without performance degradation. It is shown in the experiments that by skipping the time-consuming normalization step, the processing speed of HOG feature extraction can be significantly improved.
{"title":"Histogram of Oriented Gradients Feature Extraction Without Normalization","authors":"Ling Zhang, Weihong Zhou, Jingwei Li, Juan Li, Xin Lou","doi":"10.1109/APCCAS50809.2020.9301715","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301715","url":null,"abstract":"In this paper, the effects of normalization in the histogram of oriented gradients (HOG) are studied and a HOG feature extraction pipeline without normalization is proposed. In the proposed pipeline, the functionality of normalization is merged into the gradient generation step by replacing the original linear difference based gradients with logarithmic gradients. Due to the discrete property of the pixel values, the logarithmic operation can be easily implemented using a lookup table (LUT) with a depth of 2N, where N is the bit-width of the pixels. Theoretical analysis and experimental results show that the proposed normalization-free HOG feature based logarithmic gradient is close to the original version and can be used in the pedestrian detection algorithms without performance degradation. It is shown in the experiments that by skipping the time-consuming normalization step, the processing speed of HOG feature extraction can be significantly improved.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125057584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301692
Yuxuan Du, Xinchao Shang, Weiwei Shan
Due to the increasing demand of high energy-efficient processor for deep neural networks, traditional neural network accelerators with high-precision weights and activations that usually occupies huge on/off-chip resources with large power consumption is no longer suitable for internet-of-things applications. Binary neural networks (BNNs) reduce memory size and computation complexity, achieving drastically increased energy efficiency. In this paper, an energy-efficient time-domain binary neural network accelerator is optimized for image recognition, with time-domain accumulation (TD-MAC), timing error detection based adaptive voltage scaling design and the related approximate computing. The proposed key features are: 1) an error-tolerant adaptive voltage scaling system with TD-MAC chain truncation for aggressive power reduction, working from near-threshold to normal voltage; 2) architectural parallelism and data reuse with 100% TD-MAC utilization; 3) low power TD-MAC based on analog delay lines. Fabricated in a 28nm CMOS process, our timing error detection based adaptive voltage scaling design enables the whole system achieves a maximum 51.5TOPS/W energy efficiency at 0.42V and 25MHz, with 99.6% accuracy on MNIST dataset.
{"title":"An Energy-Efficient Time-Domain Binary Neural Network Accelerator with Error-Detection in 28nm CMOS","authors":"Yuxuan Du, Xinchao Shang, Weiwei Shan","doi":"10.1109/APCCAS50809.2020.9301692","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301692","url":null,"abstract":"Due to the increasing demand of high energy-efficient processor for deep neural networks, traditional neural network accelerators with high-precision weights and activations that usually occupies huge on/off-chip resources with large power consumption is no longer suitable for internet-of-things applications. Binary neural networks (BNNs) reduce memory size and computation complexity, achieving drastically increased energy efficiency. In this paper, an energy-efficient time-domain binary neural network accelerator is optimized for image recognition, with time-domain accumulation (TD-MAC), timing error detection based adaptive voltage scaling design and the related approximate computing. The proposed key features are: 1) an error-tolerant adaptive voltage scaling system with TD-MAC chain truncation for aggressive power reduction, working from near-threshold to normal voltage; 2) architectural parallelism and data reuse with 100% TD-MAC utilization; 3) low power TD-MAC based on analog delay lines. Fabricated in a 28nm CMOS process, our timing error detection based adaptive voltage scaling design enables the whole system achieves a maximum 51.5TOPS/W energy efficiency at 0.42V and 25MHz, with 99.6% accuracy on MNIST dataset.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115512199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The system integration of the energy devices is the challenge that constrained the development of the sustainable energy in real. This study proposed an Energy Operating System (EOS) to monitor and manage the energy devices inside the proposed energy grid node. The EOS treats the energy devices as the uniformly interfaced devices based on the proposed USB interface and the electric power line. The eight general utilization scenarios of the proposed local energy grid node system were evaluated, and the experimental results demonstrated the practicality.
{"title":"An Energy Operating System Adaptive for The Sustainable And Green Energy","authors":"Yen-Bor Lin, Chih-Chieh Ma, Chong-Cheng Hsu, Ting-Chia Ou, Tsung-Chieh Cheng, Wen-Fu Chen","doi":"10.1109/APCCAS50809.2020.9301701","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301701","url":null,"abstract":"The system integration of the energy devices is the challenge that constrained the development of the sustainable energy in real. This study proposed an Energy Operating System (EOS) to monitor and manage the energy devices inside the proposed energy grid node. The EOS treats the energy devices as the uniformly interfaced devices based on the proposed USB interface and the electric power line. The eight general utilization scenarios of the proposed local energy grid node system were evaluated, and the experimental results demonstrated the practicality.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129281675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301699
Alex Marionne A. del Castillo, Ramon G. Garcia, F. Cruz
Improving the cycle time through the development of techniques and enhancement of equipment aims customer satisfaction. Repetitive mounting and demounting on an evaluation board is one of the aspects that cause high cycle time. The open-top socketed evaluation board will be used for bench testing and fault localization eliminating the mounting and demounting process on the failure analysis flow of a specific GaAs radio frequency device and lessen the cycle time from sample preparation for failure verification until fault localization. The open-top socketed evaluation board achieved electrical specification parameters by the datasheet including supply current, gain, input and output return loss; matched emission sites on fault localization by LEM; eliminated mounting and demounting process, and saved 50.71 % of the processing time from sample preparation for failure verification up to sample preparation for physical analysis.
{"title":"Open Top Socketed Evaluation Board for Bench Test and Fault Localization on GaAs RF Device","authors":"Alex Marionne A. del Castillo, Ramon G. Garcia, F. Cruz","doi":"10.1109/APCCAS50809.2020.9301699","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301699","url":null,"abstract":"Improving the cycle time through the development of techniques and enhancement of equipment aims customer satisfaction. Repetitive mounting and demounting on an evaluation board is one of the aspects that cause high cycle time. The open-top socketed evaluation board will be used for bench testing and fault localization eliminating the mounting and demounting process on the failure analysis flow of a specific GaAs radio frequency device and lessen the cycle time from sample preparation for failure verification until fault localization. The open-top socketed evaluation board achieved electrical specification parameters by the datasheet including supply current, gain, input and output return loss; matched emission sites on fault localization by LEM; eliminated mounting and demounting process, and saved 50.71 % of the processing time from sample preparation for failure verification up to sample preparation for physical analysis.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130605356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301667
G. Sathwik, B. Acharya, Bilal Ali, P. DeepuS., D. S. Sumam
In this paper, hardware design and implementation to realize the effect of 3D sound with time-varying FIR filters are presented. 3D sound is a type of audio that encapsulates and recreates the effect identical to the way our ears normally experience. The spatial location of sound results in its three dimensional aspect. To synthesize it from a stereo recording, Head Related Transfer Functions (HRTFs), which describe the spectral behaviour of sounds coming from a particular direction are used. FIR filters derived from this transfer function are applied to the incoming sound, yielding spatial effect. The system was implemented using 180 nm technology libraries targeting an Application Specific Integrated Circuit (ASIC) and the functionality was validated in real-time on FPGA.
{"title":"Real-Time Hardware Implementation of 3D Sound Synthesis","authors":"G. Sathwik, B. Acharya, Bilal Ali, P. DeepuS., D. S. Sumam","doi":"10.1109/APCCAS50809.2020.9301667","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301667","url":null,"abstract":"In this paper, hardware design and implementation to realize the effect of 3D sound with time-varying FIR filters are presented. 3D sound is a type of audio that encapsulates and recreates the effect identical to the way our ears normally experience. The spatial location of sound results in its three dimensional aspect. To synthesize it from a stereo recording, Head Related Transfer Functions (HRTFs), which describe the spectral behaviour of sounds coming from a particular direction are used. FIR filters derived from this transfer function are applied to the incoming sound, yielding spatial effect. The system was implemented using 180 nm technology libraries targeting an Application Specific Integrated Circuit (ASIC) and the functionality was validated in real-time on FPGA.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121634225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301655
Zhechong Lan, Li Dong, Xixin Jing, Liheng Liu, Ken Li, Ziyan Shen, Zhiming Li, Li Geng
This paper presents a two-step 12-bit successive-approximation register (SAR) analog to-digital converter (ADC) with a synchronous Dynamic-Element-Matching (DEM) algorithm calibration. In the proposed two-step structure, the high-precision comparison is replaced by a low-power comparison in some conversion cycles, which can lower the power consumption of the ADC. The DEM calibration fits the 2-step structure very well and achieves a first-order mismatch shaping with negligible extra power loss. The proposed SAR ADC is fabricated in a standard 180 nm CMOS technology with a core area of 0.226 mm2. It consumes 9.15 μW at 200 kS/s sampling rate, resulting a power consumption reduction of 15%, and achieves a SNDR of 68.85 dB. The resulting figure of merit (FoM) is 20.13 fJ/conversion-step.
{"title":"A Two-step SAR ADC with Synchronous DEM Calibration Achieving Up to 15% Power Reduction","authors":"Zhechong Lan, Li Dong, Xixin Jing, Liheng Liu, Ken Li, Ziyan Shen, Zhiming Li, Li Geng","doi":"10.1109/APCCAS50809.2020.9301655","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301655","url":null,"abstract":"This paper presents a two-step 12-bit successive-approximation register (SAR) analog to-digital converter (ADC) with a synchronous Dynamic-Element-Matching (DEM) algorithm calibration. In the proposed two-step structure, the high-precision comparison is replaced by a low-power comparison in some conversion cycles, which can lower the power consumption of the ADC. The DEM calibration fits the 2-step structure very well and achieves a first-order mismatch shaping with negligible extra power loss. The proposed SAR ADC is fabricated in a standard 180 nm CMOS technology with a core area of 0.226 mm2. It consumes 9.15 μW at 200 kS/s sampling rate, resulting a power consumption reduction of 15%, and achieves a SNDR of 68.85 dB. The resulting figure of merit (FoM) is 20.13 fJ/conversion-step.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134062715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301651
Thinh Tran-Dinh, H. Pham, B. Dao, Hien Hoang-Thi, L. Pham-Nguyen, Sang-Gug Lee, Hanh-Phuc Le
This paper presents a low-power power management IC (PMIC) for Thermal Electric Generator (TEG) applications that includes investigation, demonstration, and comparison between two hybrid DC-DC converters. Both converters employs an input inductive step-up stage and an output switched-capacitor stage. The first converter, a 2-stage boost converter (2SBC), has a Boost stage connected in series with a switched-capacitor doubler, fully integrated with all control and regulation circuits. The second converter is an open-loop three-level boost converter (3LBC). Both converters are designed in a single prototype chip, fabricated in a 180-nm process. The PMIC’s self-start operation is verified at a minimum voltage of 50mV. The functionality of both converters are verified to match with simulation results, achieving above 50% efficiency for a wide range of loads. The peak efficiencies of 65% and 83% are achieved for the 2-stage boost converter and the three level boost converter at 150mV and 180mV input voltages, respectively.
{"title":"Low-Power PMIC with Two Hybrid Converters for TEG Application","authors":"Thinh Tran-Dinh, H. Pham, B. Dao, Hien Hoang-Thi, L. Pham-Nguyen, Sang-Gug Lee, Hanh-Phuc Le","doi":"10.1109/APCCAS50809.2020.9301651","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301651","url":null,"abstract":"This paper presents a low-power power management IC (PMIC) for Thermal Electric Generator (TEG) applications that includes investigation, demonstration, and comparison between two hybrid DC-DC converters. Both converters employs an input inductive step-up stage and an output switched-capacitor stage. The first converter, a 2-stage boost converter (2SBC), has a Boost stage connected in series with a switched-capacitor doubler, fully integrated with all control and regulation circuits. The second converter is an open-loop three-level boost converter (3LBC). Both converters are designed in a single prototype chip, fabricated in a 180-nm process. The PMIC’s self-start operation is verified at a minimum voltage of 50mV. The functionality of both converters are verified to match with simulation results, achieving above 50% efficiency for a wide range of loads. The peak efficiencies of 65% and 83% are achieved for the 2-stage boost converter and the three level boost converter at 150mV and 180mV input voltages, respectively.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131687610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301716
Guowei Chen, C. D. Bui, Xinyang Yu, Md. Zahidul Islam, A. Kobayashi, K. Niitsu
This paper presents a time register that uses a gated delay pipeline, to hold or propagate time information through the line by a stacked NMOS switch. The minimum supply voltage can be down to 440 mV, which is much lower than previous state-of-the-arts whose supply voltage is 1 V or higher, making this design beneficial for wearable/implantable devices in biomedical applications. The post-layout simulation performed in 65-nm CMOS technology confirms the function of the proposed time register at a conversion rate of 10 MSamples/s. The stacked-NMOS-switched architecture contributes to low leakage current, realizing low power consumption of 72 nW. In addition, the coefficient of determination, denoted R2, is 0.9956 in the linear input range of 4–11 ns, indicating good linearity.
{"title":"A 72-nW 440-mV Time Register Using Stacked-NMOS-Switched Gated Delay Cell in Biomedical Applications","authors":"Guowei Chen, C. D. Bui, Xinyang Yu, Md. Zahidul Islam, A. Kobayashi, K. Niitsu","doi":"10.1109/APCCAS50809.2020.9301716","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301716","url":null,"abstract":"This paper presents a time register that uses a gated delay pipeline, to hold or propagate time information through the line by a stacked NMOS switch. The minimum supply voltage can be down to 440 mV, which is much lower than previous state-of-the-arts whose supply voltage is 1 V or higher, making this design beneficial for wearable/implantable devices in biomedical applications. The post-layout simulation performed in 65-nm CMOS technology confirms the function of the proposed time register at a conversion rate of 10 MSamples/s. The stacked-NMOS-switched architecture contributes to low leakage current, realizing low power consumption of 72 nW. In addition, the coefficient of determination, denoted R2, is 0.9956 in the linear input range of 4–11 ns, indicating good linearity.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133723824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301675
Jianglin Wei, A. Kuwana, Haruo Kobayashi, K. Kubo
This paper investigates floating-point division algorithms based on Taylor-series expansion. Taylor-series expansions of 1/x are examined for several center points with their convergence ranges, and show the Taylor-series expansion division algorithm trade-offs among division accuracy, numbers of multiplications/additions/subtractions and LUT sizes; the designer can choose the optimal algorithm for his digital division, and build its conceptual architecture design with the contents described here.
{"title":"Revisit to Floating-Point Division Algorithm Based on Taylor-Series Expansion","authors":"Jianglin Wei, A. Kuwana, Haruo Kobayashi, K. Kubo","doi":"10.1109/APCCAS50809.2020.9301675","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301675","url":null,"abstract":"This paper investigates floating-point division algorithms based on Taylor-series expansion. Taylor-series expansions of 1/x are examined for several center points with their convergence ranges, and show the Taylor-series expansion division algorithm trade-offs among division accuracy, numbers of multiplications/additions/subtractions and LUT sizes; the designer can choose the optimal algorithm for his digital division, and build its conceptual architecture design with the contents described here.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117287659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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