Ryan Lund, Connor McMahon, Daniel D. Garcia, B. Nikolić
{"title":"Improved Processor Design Project Testing","authors":"Ryan Lund, Connor McMahon, Daniel D. Garcia, B. Nikolić","doi":"10.1109/WCAE53984.2021.9707152","DOIUrl":null,"url":null,"abstract":"Introductory-level computer architecture courses often rely on programs with a graphical user interface (such as Logisim) for processor design projects. While these tools provide an easy introduction into logic design, they can detach students from real-world design constraints such as ISA standard tests, and real-world ramifications such as timing and area. This paper introduces a testing flow based on open-source tools that allows Logisim-based designs to be built into ISA-test-compatible simulation binaries, synthesized into gate netlists, and compared for similarity. This flow was used in UC Berkeley’s fall 2020 Great Ideas of Computer Architecture course; out of 695 project submissions, over 96% achieved highly-functional designs as measured by the presented infrastructure. CCS CONCEPTS •Social and professional topics $\\rightarrow$ Computer engineering education; •Computer systems organization $\\rightarrow$ Reduced instruction set computing; Pipeline computing. ACM Reference Format: Ryan Lund, Connor McMahon, Dan Garcia, and Borivoje Nikolić. 2021. Improved Processor Design Project Testing. In Proceedings of WCAE ’21. ACM, New York, NY, USA, 7 pages. https://doi.org/10.1145/1122445.1122456","PeriodicalId":186301,"journal":{"name":"2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/WCAE53984.2021.9707152","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Introductory-level computer architecture courses often rely on programs with a graphical user interface (such as Logisim) for processor design projects. While these tools provide an easy introduction into logic design, they can detach students from real-world design constraints such as ISA standard tests, and real-world ramifications such as timing and area. This paper introduces a testing flow based on open-source tools that allows Logisim-based designs to be built into ISA-test-compatible simulation binaries, synthesized into gate netlists, and compared for similarity. This flow was used in UC Berkeley’s fall 2020 Great Ideas of Computer Architecture course; out of 695 project submissions, over 96% achieved highly-functional designs as measured by the presented infrastructure. CCS CONCEPTS •Social and professional topics $\rightarrow$ Computer engineering education; •Computer systems organization $\rightarrow$ Reduced instruction set computing; Pipeline computing. ACM Reference Format: Ryan Lund, Connor McMahon, Dan Garcia, and Borivoje Nikolić. 2021. Improved Processor Design Project Testing. In Proceedings of WCAE ’21. ACM, New York, NY, USA, 7 pages. https://doi.org/10.1145/1122445.1122456