Pub Date : 2021-06-17DOI: 10.1109/WCAE53984.2021.9707147
Ellen Spertus, Zachary Kurmas
Mastery-based learning is an approach in which students are graded based on their demonstrated mastery of explicit learning outcomes rather than by being awarded points less directly connected to course goals. Instead of submitting an assignment only once, students can use feedback to improve their work to increase their learning and grades. We describe our approach to mastery-based grading in introductory computer organization/architecture courses at two different institutions. Specifically, we allowed students to retake tests of basic skills as many times as needed, which was facilitated by programmatically-generated questions. For course projects, students were expected to refine and resubmit projects until they demonstrated mastery by passing all of the provided automated tests. We share our materials and experiences, including the challenge of loosening deadlines to provide students time for continued work without enabling them to fall irretrievably behind.CCS CONCEPTS• Applied computing $rightarrow$ Interactive learning environments; Computer-assisted instruction; • Social and professional topics $rightarrow$ Computer science education; Student assessment; • Computer systems organization $rightarrow$ Architectures. ACM Reference Format:Ellen Spertus and Zachary Kurmas. 2021. Mastery-Based Learning in Undergraduate Computer Architecture. In Proceedings of Workshop on Computer Architecture Education 2021 (WCAE ’21). ACM, New York, NY, USA, 7 pages. https://doi.org/10.1145/nnnnnnn.nnnnnnn
{"title":"Mastery-Based Learning in Undergraduate Computer Architecture","authors":"Ellen Spertus, Zachary Kurmas","doi":"10.1109/WCAE53984.2021.9707147","DOIUrl":"https://doi.org/10.1109/WCAE53984.2021.9707147","url":null,"abstract":"Mastery-based learning is an approach in which students are graded based on their demonstrated mastery of explicit learning outcomes rather than by being awarded points less directly connected to course goals. Instead of submitting an assignment only once, students can use feedback to improve their work to increase their learning and grades. We describe our approach to mastery-based grading in introductory computer organization/architecture courses at two different institutions. Specifically, we allowed students to retake tests of basic skills as many times as needed, which was facilitated by programmatically-generated questions. For course projects, students were expected to refine and resubmit projects until they demonstrated mastery by passing all of the provided automated tests. We share our materials and experiences, including the challenge of loosening deadlines to provide students time for continued work without enabling them to fall irretrievably behind.CCS CONCEPTS• Applied computing $rightarrow$ Interactive learning environments; Computer-assisted instruction; • Social and professional topics $rightarrow$ Computer science education; Student assessment; • Computer systems organization $rightarrow$ Architectures. ACM Reference Format:Ellen Spertus and Zachary Kurmas. 2021. Mastery-Based Learning in Undergraduate Computer Architecture. In Proceedings of Workshop on Computer Architecture Education 2021 (WCAE ’21). ACM, New York, NY, USA, 7 pages. https://doi.org/10.1145/nnnnnnn.nnnnnnn","PeriodicalId":186301,"journal":{"name":"2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131542835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-17DOI: 10.1109/WCAE53984.2021.9707150
Ellen Spertus
The COVID-19 pandemic necessitated courses being moved online and preferably made asynchronous. This was particularly challenging for small liberal arts colleges, whose faculty and students are used to close interaction. This paper describes the set of interactive asynchronous mini-lectures and online lab assignments used for an undergraduate computer architecture course at Mills College. The materials, which follow best practices for active learning, are available online for faculty at other institutions to use and modify under a Creative Commons license. We also discuss the pros and cons of making the course self-paced.CCS CONCEPTS• Applied computing → E-learning; Interactive learning environments; • Social and professional topics → Computer science education.ACM Reference Format:Ellen Spertus. 2021. Interactive Asynchronous Online Computer Architecture Education. In Proceedings of Workshop on Computer Architecture Education 2021 (WCAE ’21). ACM, New York, NY, USA, 8 pages. https: //doi.org/10.1145/nnnnnnn.nnnnnnn
{"title":"Interactive Asynchronous Online Computer Architecture Education","authors":"Ellen Spertus","doi":"10.1109/WCAE53984.2021.9707150","DOIUrl":"https://doi.org/10.1109/WCAE53984.2021.9707150","url":null,"abstract":"The COVID-19 pandemic necessitated courses being moved online and preferably made asynchronous. This was particularly challenging for small liberal arts colleges, whose faculty and students are used to close interaction. This paper describes the set of interactive asynchronous mini-lectures and online lab assignments used for an undergraduate computer architecture course at Mills College. The materials, which follow best practices for active learning, are available online for faculty at other institutions to use and modify under a Creative Commons license. We also discuss the pros and cons of making the course self-paced.CCS CONCEPTS• Applied computing → E-learning; Interactive learning environments; • Social and professional topics → Computer science education.ACM Reference Format:Ellen Spertus. 2021. Interactive Asynchronous Online Computer Architecture Education. In Proceedings of Workshop on Computer Architecture Education 2021 (WCAE ’21). ACM, New York, NY, USA, 8 pages. https: //doi.org/10.1145/nnnnnnn.nnnnnnn","PeriodicalId":186301,"journal":{"name":"2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126089235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-17DOI: 10.1109/WCAE53984.2021.9707146
Matthias Koenig, Robin Rasch
In this paper, we discuss how an embedded system course was transferred from classroom teaching to digital teaching using simulation tools instead of physical embedded systems hardware in a computer science undergraduate studies at the Bielefeld University of Applied Sciences. We aligned our teaching to RISC-V based hard- and software as we have seen advantages due to open source. Our approach is described and the evaluation of the course by our students is given and discussed.CCS CONCEPTS• Social and professional topics $rightarrow$ Computing education;• Computer systems organization $rightarrow$ Embedded systems.ACM Reference Format:Matthias Koenig and Robin Rasch. 2021. Digital Teaching an Embedded Systems Course by Using Simulators. In WCAE ’21: Workshop on Computer Architecture Education, June 71, 2021, Online. ACM, New York, NY, USA, 7 pages.
{"title":"Digital Teaching an Embedded Systems Course by Using Simulators","authors":"Matthias Koenig, Robin Rasch","doi":"10.1109/WCAE53984.2021.9707146","DOIUrl":"https://doi.org/10.1109/WCAE53984.2021.9707146","url":null,"abstract":"In this paper, we discuss how an embedded system course was transferred from classroom teaching to digital teaching using simulation tools instead of physical embedded systems hardware in a computer science undergraduate studies at the Bielefeld University of Applied Sciences. We aligned our teaching to RISC-V based hard- and software as we have seen advantages due to open source. Our approach is described and the evaluation of the course by our students is given and discussed.CCS CONCEPTS• Social and professional topics $rightarrow$ Computing education;• Computer systems organization $rightarrow$ Embedded systems.ACM Reference Format:Matthias Koenig and Robin Rasch. 2021. Digital Teaching an Embedded Systems Course by Using Simulators. In WCAE ’21: Workshop on Computer Architecture Education, June 71, 2021, Online. ACM, New York, NY, USA, 7 pages.","PeriodicalId":186301,"journal":{"name":"2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115646914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-17DOI: 10.1109/WCAE53984.2021.9707152
Ryan Lund, Connor McMahon, Daniel D. Garcia, B. Nikolić
Introductory-level computer architecture courses often rely on programs with a graphical user interface (such as Logisim) for processor design projects. While these tools provide an easy introduction into logic design, they can detach students from real-world design constraints such as ISA standard tests, and real-world ramifications such as timing and area. This paper introduces a testing flow based on open-source tools that allows Logisim-based designs to be built into ISA-test-compatible simulation binaries, synthesized into gate netlists, and compared for similarity. This flow was used in UC Berkeley’s fall 2020 Great Ideas of Computer Architecture course; out of 695 project submissions, over 96% achieved highly-functional designs as measured by the presented infrastructure. CCS CONCEPTS •Social and professional topics $rightarrow$ Computer engineering education; •Computer systems organization $rightarrow$ Reduced instruction set computing; Pipeline computing. ACM Reference Format: Ryan Lund, Connor McMahon, Dan Garcia, and Borivoje Nikolić. 2021. Improved Processor Design Project Testing. In Proceedings of WCAE ’21. ACM, New York, NY, USA, 7 pages. https://doi.org/10.1145/1122445.1122456
{"title":"Improved Processor Design Project Testing","authors":"Ryan Lund, Connor McMahon, Daniel D. Garcia, B. Nikolić","doi":"10.1109/WCAE53984.2021.9707152","DOIUrl":"https://doi.org/10.1109/WCAE53984.2021.9707152","url":null,"abstract":"Introductory-level computer architecture courses often rely on programs with a graphical user interface (such as Logisim) for processor design projects. While these tools provide an easy introduction into logic design, they can detach students from real-world design constraints such as ISA standard tests, and real-world ramifications such as timing and area. This paper introduces a testing flow based on open-source tools that allows Logisim-based designs to be built into ISA-test-compatible simulation binaries, synthesized into gate netlists, and compared for similarity. This flow was used in UC Berkeley’s fall 2020 Great Ideas of Computer Architecture course; out of 695 project submissions, over 96% achieved highly-functional designs as measured by the presented infrastructure. CCS CONCEPTS •Social and professional topics $rightarrow$ Computer engineering education; •Computer systems organization $rightarrow$ Reduced instruction set computing; Pipeline computing. ACM Reference Format: Ryan Lund, Connor McMahon, Dan Garcia, and Borivoje Nikolić. 2021. Improved Processor Design Project Testing. In Proceedings of WCAE ’21. ACM, New York, NY, USA, 7 pages. https://doi.org/10.1145/1122445.1122456","PeriodicalId":186301,"journal":{"name":"2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125856969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-17DOI: 10.1109/WCAE53984.2021.9707144
Stefan Wallentowitz
It is the golden age of practical computer architecture. The rise of open source hardware designs and the open RISC-V instruction set architecture enables us to build courses around real processor cores of varying complexity. While it is desirable to build lab assignments and projects around actual processors, the common presentation of hardware designs in the form of waveforms is not very accessible to students, especially outside of EE. In this paper I present an open source framework for microarchitectural traces along with a simple but efficient visualization tool called pipeline-viewer. It is targeted at computer architecture classes where microarchitecture details are taught and real world demonstration is helpful.ACM Reference Format:Stefan Wallentowitz. 2021. A Framework for Microarchitecture Traces as Abstraction Layer in Computer Architecture Education. In Proceedings of WCAE 2021: Workshop on Computer Architecture Education (WCAE 2021). ACM, New York, NY, USA, 7 pages. https://doi.org/10.1145/nnnnnnn.nnnnnnn
{"title":"A Framework for Microarchitecture Traces as Abstraction Layer in Computer Architecture Education","authors":"Stefan Wallentowitz","doi":"10.1109/WCAE53984.2021.9707144","DOIUrl":"https://doi.org/10.1109/WCAE53984.2021.9707144","url":null,"abstract":"It is the golden age of practical computer architecture. The rise of open source hardware designs and the open RISC-V instruction set architecture enables us to build courses around real processor cores of varying complexity. While it is desirable to build lab assignments and projects around actual processors, the common presentation of hardware designs in the form of waveforms is not very accessible to students, especially outside of EE. In this paper I present an open source framework for microarchitectural traces along with a simple but efficient visualization tool called pipeline-viewer. It is targeted at computer architecture classes where microarchitecture details are taught and real world demonstration is helpful.ACM Reference Format:Stefan Wallentowitz. 2021. A Framework for Microarchitecture Traces as Abstraction Layer in Computer Architecture Education. In Proceedings of WCAE 2021: Workshop on Computer Architecture Education (WCAE 2021). ACM, New York, NY, USA, 7 pages. https://doi.org/10.1145/nnnnnnn.nnnnnnn","PeriodicalId":186301,"journal":{"name":"2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130386298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-17DOI: 10.1109/WCAE53984.2021.9707143
Stephen A. Zekany, Jielun Tan, James A. Connolly
We describe our experience teaching an undergraduate capstone (and elective graduate course) in computer architecture with a semester-long project in which teams of five students design and implement an out-of-order (OoO) pipelined processor core using the open-source RISC-V instruction set. The course content includes OoO scheduling algorithms for instructions to exploit instruction-level parallelism (ILP), example designs, caching, prefetching, and virtual memory. The labs and projects help students gain proficiency with the SystemVerilog language.Students use the concepts learned in class to design processors with the goals of achieving correctness and high performance for a suite of representative test programs. Using RISC-V enables students to validate and benchmark their designs by compiling test programs using GCC with a custom linker. By collaborating as a team, students learn how to write and debug a large code base over the two-month project.For computer architecture educators, we describe technical aspects of the final project and common advanced features implemented by students. We hope describing our experience serves not only to demonstrate a method of teaching modern computer architecture, but also to inspire other course designs centered around other aspects of modern computer architecture (GPUs, FPGAs, hardware/software codesign, etc). We have open-sourced our lab and project materials to enable others to teach similar courses.CCS CONCEPTS• Social and professional topics → Computer engineering education.ACM Reference Format:Stephen A. Zekany, Jielun Tan, James A. Connolly, and Ronald G. Dreslinski. 2021. Teaching Out-of-Order Processor Design with the RISC-V ISA. In ISCA Workshop on Computer Architecture Education (WCAE ’21), June 17, 2021, Virtual Event, USA. ACM, New York, NY, USA, 8 pages. https://doi.org/10.1145/nnnnnnn.nnnnnnn
我们用一个学期的项目来描述我们教授计算机体系结构本科顶点课程(和选修研究生课程)的经验，在这个项目中，五名学生组成的团队使用开源的RISC-V指令集设计和实现了一个无序(OoO)流水线处理器核心。课程内容包括利用指令级并行性(ILP)的OoO指令调度算法、示例设计、缓存、预取和虚拟内存。这些实验室和项目帮助学生熟练掌握SystemVerilog语言。学生使用在课堂上学到的概念来设计处理器，以实现一套代表性测试程序的正确性和高性能。使用RISC-V使学生能够通过使用带有自定义链接器的GCC编译测试程序来验证和基准测试他们的设计。通过作为一个团队合作，学生将在两个月的项目中学习如何编写和调试大型代码库。对于计算机体系结构教育者，我们描述了最终项目的技术方面和学生实现的常见高级功能。我们希望描述我们的经验不仅可以展示一种教授现代计算机体系结构的方法，还可以启发围绕现代计算机体系结构(gpu, fpga，硬件/软件协同设计等)的其他方面的课程设计。我们已经开源了我们的实验和项目材料，使其他人能够教授类似的课程。•社会和专业主题→计算机工程教育。ACM参考格式:Stephen A. Zekany, Jielun Tan, James A. Connolly和Ronald G. Dreslinski。2021。用RISC-V ISA教学乱序处理器设计。在ISCA计算机体系结构教育研讨会(WCAE ' 21)， 2021年6月17日，虚拟事件，美国。ACM，纽约，美国，8页。https://doi.org/10.1145/nnnnnnn.nnnnnnn
{"title":"Teaching Out-of-Order Processor Design with the RISC-V ISA","authors":"Stephen A. Zekany, Jielun Tan, James A. Connolly","doi":"10.1109/WCAE53984.2021.9707143","DOIUrl":"https://doi.org/10.1109/WCAE53984.2021.9707143","url":null,"abstract":"We describe our experience teaching an undergraduate capstone (and elective graduate course) in computer architecture with a semester-long project in which teams of five students design and implement an out-of-order (OoO) pipelined processor core using the open-source RISC-V instruction set. The course content includes OoO scheduling algorithms for instructions to exploit instruction-level parallelism (ILP), example designs, caching, prefetching, and virtual memory. The labs and projects help students gain proficiency with the SystemVerilog language.Students use the concepts learned in class to design processors with the goals of achieving correctness and high performance for a suite of representative test programs. Using RISC-V enables students to validate and benchmark their designs by compiling test programs using GCC with a custom linker. By collaborating as a team, students learn how to write and debug a large code base over the two-month project.For computer architecture educators, we describe technical aspects of the final project and common advanced features implemented by students. We hope describing our experience serves not only to demonstrate a method of teaching modern computer architecture, but also to inspire other course designs centered around other aspects of modern computer architecture (GPUs, FPGAs, hardware/software codesign, etc). We have open-sourced our lab and project materials to enable others to teach similar courses.CCS CONCEPTS• Social and professional topics → Computer engineering education.ACM Reference Format:Stephen A. Zekany, Jielun Tan, James A. Connolly, and Ronald G. Dreslinski. 2021. Teaching Out-of-Order Processor Design with the RISC-V ISA. In ISCA Workshop on Computer Architecture Education (WCAE ’21), June 17, 2021, Virtual Event, USA. ACM, New York, NY, USA, 8 pages. https://doi.org/10.1145/nnnnnnn.nnnnnnn","PeriodicalId":186301,"journal":{"name":"2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126496845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-17DOI: 10.1109/WCAE53984.2021.9707151
Charlie Curtsinger, Jerod J. Weinman
CSC 211: Computer Organization and Architecture at Grinnell College introduces computer science students to the basics of digital circuits, logic design, and computer organization/architecture. This course is designed to help students develop a deeper understanding of how processors function, and how their design can impact the code they write. During the course, students build components like adders, multiplexors, ALUs, and registers with real circuits, and larger components in a digital logic simulator (Logisim). This progression culminates in a four-week lab sequence where students create an assembler and datapath for the PIPS Instruction Set Architecture, which we have designed specifically for this course. In this paper we describe the design and specific learning goals of the PIPS architecture, the four-week lab sequence where students implement a working PIPS assembler and datapath, and our experiences using this lab sequence for the past three years. All student starter materials and instructions for these labs are available at DOI:11084/10426, with solutions and grading infrastructure available to instructors upon request. CCS CONCEPTS • Computer systems organization $rightarrow$ Reduced instruction set computing; • Applied computing $rightarrow$ Education.ACM Reference Format: Charlie Curtsinger and Jerod Weinman. 2021. PIPS: An Instruction Set Architecture for Teaching Computer Organization. In WCAE ’21: Workshop on Computer Architecture Education, June 17, 2021. ACM, New York, NY, USA, 8 pages. https://doi.org/11084/10437
{"title":"PIPS: An Instruction Set Architecture for Teaching Computer Organization","authors":"Charlie Curtsinger, Jerod J. Weinman","doi":"10.1109/WCAE53984.2021.9707151","DOIUrl":"https://doi.org/10.1109/WCAE53984.2021.9707151","url":null,"abstract":"CSC 211: Computer Organization and Architecture at Grinnell College introduces computer science students to the basics of digital circuits, logic design, and computer organization/architecture. This course is designed to help students develop a deeper understanding of how processors function, and how their design can impact the code they write. During the course, students build components like adders, multiplexors, ALUs, and registers with real circuits, and larger components in a digital logic simulator (Logisim). This progression culminates in a four-week lab sequence where students create an assembler and datapath for the PIPS Instruction Set Architecture, which we have designed specifically for this course. In this paper we describe the design and specific learning goals of the PIPS architecture, the four-week lab sequence where students implement a working PIPS assembler and datapath, and our experiences using this lab sequence for the past three years. All student starter materials and instructions for these labs are available at DOI:11084/10426, with solutions and grading infrastructure available to instructors upon request. CCS CONCEPTS • Computer systems organization $rightarrow$ Reduced instruction set computing; • Applied computing $rightarrow$ Education.ACM Reference Format: Charlie Curtsinger and Jerod Weinman. 2021. PIPS: An Instruction Set Architecture for Teaching Computer Organization. In WCAE ’21: Workshop on Computer Architecture Education, June 17, 2021. ACM, New York, NY, USA, 8 pages. https://doi.org/11084/10437","PeriodicalId":186301,"journal":{"name":"2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129892525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-17DOI: 10.1109/WCAE53984.2021.9707614
Elba Garza, Gururaj Saileshwar, Udit Gupta, Tianyi Liu, A. Mahmoud, Saugata Ghose, Joel S. Emer
Academic mentoring programming is a powerful tool used for supporting, engaging, and retaining students in their fields of study. Researchers have long known the positive effects of academic mentoring, particularly for students from underrepresented and marginalized backgrounds. The computer architecture community currently hosts an assortment of mentoring programs geared toward women, underrepresented students, junior graduate students, and undergraduates alike.In this work, we describe the current state of mentoring opportunities for students in computer architecture. In addition to summarizing various mentoring programs (e.g., CWWMCA, YArch, and uArch), this work details the organization and feedback from two programs (MaSA and MaSS) that the authors currently run and organize. Based on feedback from these short-term mentoring programs, along with relevant mentoring research literature, we identify opportunities for developing more productive longer-term mentoring programming for the computer architecture community. Following mentoring literature, this work makes a strong case for offering both short-term and long-term mentoring programs in the future; in particular, mentoring literature show the need for time in forming mentoring relationships for mentees to receive the multifaceted benefits of mentoring.ACM Reference Format:Elba Garza, Gururaj Saileshwar, Udit Gupta, Tianyi Liu, Abdulrahman Mahmoud, Saugata Ghose, and Joel Emer. 2021. Mentoring Opportunities in Computer Architecture: Analyzing the Past to Develop the Future. In WCAE ’21: Workshop on Computer Architecture Education, June 17,2021, Online. ACM, New York, NY, USA, 9 pages. https://doi.org/10.1145/nnnnnnn.nnnnnnn
{"title":"Mentoring Opportunities in Computer Architecture: Analyzing the Past to Develop the Future","authors":"Elba Garza, Gururaj Saileshwar, Udit Gupta, Tianyi Liu, A. Mahmoud, Saugata Ghose, Joel S. Emer","doi":"10.1109/WCAE53984.2021.9707614","DOIUrl":"https://doi.org/10.1109/WCAE53984.2021.9707614","url":null,"abstract":"Academic mentoring programming is a powerful tool used for supporting, engaging, and retaining students in their fields of study. Researchers have long known the positive effects of academic mentoring, particularly for students from underrepresented and marginalized backgrounds. The computer architecture community currently hosts an assortment of mentoring programs geared toward women, underrepresented students, junior graduate students, and undergraduates alike.In this work, we describe the current state of mentoring opportunities for students in computer architecture. In addition to summarizing various mentoring programs (e.g., CWWMCA, YArch, and uArch), this work details the organization and feedback from two programs (MaSA and MaSS) that the authors currently run and organize. Based on feedback from these short-term mentoring programs, along with relevant mentoring research literature, we identify opportunities for developing more productive longer-term mentoring programming for the computer architecture community. Following mentoring literature, this work makes a strong case for offering both short-term and long-term mentoring programs in the future; in particular, mentoring literature show the need for time in forming mentoring relationships for mentees to receive the multifaceted benefits of mentoring.ACM Reference Format:Elba Garza, Gururaj Saileshwar, Udit Gupta, Tianyi Liu, Abdulrahman Mahmoud, Saugata Ghose, and Joel Emer. 2021. Mentoring Opportunities in Computer Architecture: Analyzing the Past to Develop the Future. In WCAE ’21: Workshop on Computer Architecture Education, June 17,2021, Online. ACM, New York, NY, USA, 9 pages. https://doi.org/10.1145/nnnnnnn.nnnnnnn","PeriodicalId":186301,"journal":{"name":"2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129032520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-17DOI: 10.1109/WCAE53984.2021.9707615
Sarah L. Harris, D. Harris
This paper describes the authors’ Digital Design and Computer Architecture: RISC-V Edition textbook. The book presents a unified 1-or 2-semester course on digital design and computer architecture. We have found that learning these topics together clarifies and solidifies understanding of both concepts. The textbook begins by describing digital design concepts and techniques, from number systems, logic gates, and transistor-level gate design to synchronous sequential circuits such as finite state machines and other common digital building blocks. It then builds on these concepts to teach computer architecture and processor design by introducing the RISC-V instruction set architecture (ISA), showing how to design three RISC-V processors with limited instructions, and describing various memory organizations, including caches and virtual memory. The textbook also describes logic design using hardware description languages (HDLs), covering SystemVerilog and VHDL side-by-side. The optional appendices and online chapters introduce the C programming language, embedded system design, and practical aspects of digital design including breadboarding, ASIC design, and transmission lines.CCS CONCEPTS • Architectures • Embedded Systems • Logic
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Pub Date : 2021-06-17DOI: 10.1109/WCAE53984.2021.9707149
Morten B. Petersen
Ripes is a visual computer architecture simulator built around the RISC-V ISA. The main feature of Ripes is its tight integration of a built-in assembler, compiler support, and cache simulator, all centered around a visual microarchitecture simulator. Several microarchitectural models are provided to explore the evolutions of a typical processor pipeline, such as the different iterations of processors when going from a single-cycle model to a classic RISC five-stage pipeline. This paper details the core features of Ripes, the design decisions behind them, as well as thoughts on how Ripes may fit into a larger ecosystem by joining the growing movement around open hardware toolchains. Ripes is an actively maintained open-source project and is at the time of writing used in teaching at various universities, as well as in nonacademic settings.ACM Reference Format:Morten B. Petersen. 2021. Ripes: A Visual Computer Architecture Simulator. In Proceedings of WCAE ’21: IEEE Workshop on Computer Architecture Education (WCAE ’21). ACM, New York, NY, USA, 8 pages.
Ripes是围绕RISC-V ISA构建的可视化计算机体系结构模拟器。Ripes的主要特性是它将内置汇编器、编译器支持和缓存模拟器紧密集成在一起，所有这些都围绕着一个可视化的微体系结构模拟器。提供了几个微体系结构模型来探索典型处理器管道的演变，例如从单周期模型到经典RISC五阶段管道时处理器的不同迭代。本文详细介绍了Ripes的核心特性、背后的设计决策，以及关于Ripes如何通过加入围绕开放硬件工具链的不断增长的运动来适应更大的生态系统的想法。Ripes是一个积极维护的开源项目，在各种大学的教学中使用，以及在非学术环境中使用。ACM参考格式:Morten B. Petersen。2021。Ripes:一个视觉计算机体系结构模拟器。IEEE计算机体系结构教育研讨会(WCAE ' 21)。ACM，纽约，美国，8页。
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