Testability analysis based on structural and behavioral information

Abstract

When VLSI circuits such as microprocessors are designed hierarchically, testability issues have to be considered simultaneously with functional specifications to reduce the testing complexity early in the design phase. Accurate testability measures are required to indicate the hard-to-test areas and can be used as a guidance for ATPG. This paper presents a new testability analysis technique operating at a high level using both circuit structural information and assembly-level instruction behavioral information. This testability analysis targets at the popular functional test generation and a modern high level ATPG methodology published in recent literature. The experimental results of testability measures as well as high level ATPG are presented to verify the effectiveness.<>