{"title":"Evaluation of SRAM cell write margin metrics for lifetime monitoring of BTI-induced Vth drift","authors":"B. Alorda, G. Torrens","doi":"10.1109/DTIS.2017.7930175","DOIUrl":null,"url":null,"abstract":"The Threshold voltage variability is increasing due to the process variability and reliability issues. SRAM cell stability dependence with threshold voltage is analyzed in order to extract reliability degradation due to BTI-induced Vth drift. The several write margin definitions are selected and their feasibility to be implemented in a threshold voltage built-in sensor is analyzed. The writability margins based on external cell nodes measurement have demonstrated best suitability for large memory arrays reducing the needs of hardware maintaining a good linearity for both high activity systems and long time storage.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DTIS.2017.7930175","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
The Threshold voltage variability is increasing due to the process variability and reliability issues. SRAM cell stability dependence with threshold voltage is analyzed in order to extract reliability degradation due to BTI-induced Vth drift. The several write margin definitions are selected and their feasibility to be implemented in a threshold voltage built-in sensor is analyzed. The writability margins based on external cell nodes measurement have demonstrated best suitability for large memory arrays reducing the needs of hardware maintaining a good linearity for both high activity systems and long time storage.
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