Pub Date : 2017-05-16DOI: 10.1109/DTIS.2017.7929873
Sima Sinaei, A. Pimentel, O. Fatemi
The dynamic nature of application workloads in modern MPSoC-based embedded systems is growing. To cope with the dynamism of application workloads at run time and to improve the efficiency of the underlying system architecture, this paper presents a novel run-time resource allocation algorithm for multimedia applications with the objective of minimizing energy consumption for predefined deadlines. This algorithm is based on a novel tree-based design space exploration (DSE) method, which is performed in two phases: design-time and run-time. During design time, application clustering is combined with the tree-based DSE, and after that, feature extraction and application classification is performed during run-time based on well-known machine learning techniques. We evaluated our algorithm using a heterogeneous MPSoC system with several applications that have different communication and computation behaviors. Our experimental results revealed that during runtime, more than 91% of the applications were classified correctly by our proposed algorithm to select the best resources for allocation. Therefore the results clearly confirm that our algorithm is effective.
{"title":"Run-time resource allocation for embedded Multiprocessor System-on-Chip using tree-based design space exploration","authors":"Sima Sinaei, A. Pimentel, O. Fatemi","doi":"10.1109/DTIS.2017.7929873","DOIUrl":"https://doi.org/10.1109/DTIS.2017.7929873","url":null,"abstract":"The dynamic nature of application workloads in modern MPSoC-based embedded systems is growing. To cope with the dynamism of application workloads at run time and to improve the efficiency of the underlying system architecture, this paper presents a novel run-time resource allocation algorithm for multimedia applications with the objective of minimizing energy consumption for predefined deadlines. This algorithm is based on a novel tree-based design space exploration (DSE) method, which is performed in two phases: design-time and run-time. During design time, application clustering is combined with the tree-based DSE, and after that, feature extraction and application classification is performed during run-time based on well-known machine learning techniques. We evaluated our algorithm using a heterogeneous MPSoC system with several applications that have different communication and computation behaviors. Our experimental results revealed that during runtime, more than 91% of the applications were classified correctly by our proposed algorithm to select the best resources for allocation. Therefore the results clearly confirm that our algorithm is effective.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116980907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-04-04DOI: 10.1109/DTIS.2017.7930178
M. Barbareschi, A. Bosio, Hoang Anh Du Nguyen, S. Hamdioui, Marcello Traiola, E. Vatajelu
The memristor is an emerging technology which is triggering intense interdisciplinary activity. It has the potential of providing many benefits, such as energy efficiency, density, reconfigurability, nonvolatile memory, novel computational structures and approaches, massive parallelism, etc. These characteristics may lead to deeply revise existing computing and storage paradigms. This paper presents a comprehensive overview of memristor technology and its potential to design a new computational paradigm.
{"title":"Memristive devices: Technology, design automation and computing frontiers","authors":"M. Barbareschi, A. Bosio, Hoang Anh Du Nguyen, S. Hamdioui, Marcello Traiola, E. Vatajelu","doi":"10.1109/DTIS.2017.7930178","DOIUrl":"https://doi.org/10.1109/DTIS.2017.7930178","url":null,"abstract":"The memristor is an emerging technology which is triggering intense interdisciplinary activity. It has the potential of providing many benefits, such as energy efficiency, density, reconfigurability, nonvolatile memory, novel computational structures and approaches, massive parallelism, etc. These characteristics may lead to deeply revise existing computing and storage paradigms. This paper presents a comprehensive overview of memristor technology and its potential to design a new computational paradigm.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128776435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-04-04DOI: 10.1109/DTIS.2017.7930157
F. Gossen, Johannes Neubauer, B. Steffen
In this paper we demonstrate the power and flexibility of extreme model-driven design using C-IME, our integrated modelling environment for C/C++ by showing how easily an application modelled in C-IME can be enhanced with hardware security features. In fact, our approach does not require any changes of the application model. Rather, C-IME provides a dedicated modelling language for code generators which embodies a palette of security primitives that are implemented based on the SEcube™ API. We will illustrate how the required code generator can be modelled for a to-do list management application in our case study. It should be noted that this code generator is not limited to the considered application but it can be used to secure the file handling of any application modelled in C-IME.
{"title":"Securing C/C++ applications with a SEcube™-based model-driven approach","authors":"F. Gossen, Johannes Neubauer, B. Steffen","doi":"10.1109/DTIS.2017.7930157","DOIUrl":"https://doi.org/10.1109/DTIS.2017.7930157","url":null,"abstract":"In this paper we demonstrate the power and flexibility of extreme model-driven design using C-IME, our integrated modelling environment for C/C++ by showing how easily an application modelled in C-IME can be enhanced with hardware security features. In fact, our approach does not require any changes of the application model. Rather, C-IME provides a dedicated modelling language for code generators which embodies a palette of security primitives that are implemented based on the SEcube™ API. We will illustrate how the required code generator can be modelled for a to-do list management application in our case study. It should be noted that this code generator is not limited to the considered application but it can be used to secure the file handling of any application modelled in C-IME.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129740286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-04-04DOI: 10.1109/DTIS.2017.7930181
J. Cesari, Á. Pineda, S. Danzeca, A. Masi, M. Brugger, Maria Del Mar Fernandez, E. Isern, M. Roca, E. García-Moreno
Two different structures as charge injectors for Floating Gate sensors are tested and analysed. First of all the theoretical charge injection processes are exposed and discussed. Secondly experimental results on both structures are presented. The experimental results allow to choose one of the structures as a candidate to be used embedded with the Floating Gate sensor system.
{"title":"Analysis of two different charge injector candidates for an on-chip Floating Gate recharging system","authors":"J. Cesari, Á. Pineda, S. Danzeca, A. Masi, M. Brugger, Maria Del Mar Fernandez, E. Isern, M. Roca, E. García-Moreno","doi":"10.1109/DTIS.2017.7930181","DOIUrl":"https://doi.org/10.1109/DTIS.2017.7930181","url":null,"abstract":"Two different structures as charge injectors for Floating Gate sensors are tested and analysed. First of all the theoretical charge injection processes are exposed and discussed. Secondly experimental results on both structures are presented. The experimental results allow to choose one of the structures as a candidate to be used embedded with the Floating Gate sensor system.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116251748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-04-04DOI: 10.1109/DTIS.2017.7929871
S. Cowell, L. Dăuş, Valeriu Beiu, P. Poulin
This paper considers the hammock networks introduced by Moore and Shannon in 1956. We mention reliability polynomials (including some of their properties) and go briefly over the state-of-the-art: theoretical, algorithmic and design oriented. These are advocating for using (small) hammock networks as a perfect fit for array-based designs of nano-devices (like, e.g., FinFETs, SegFETs, VFETs, VeSFETs, and various nanotubes transistors). Because array-based designs are expected to thrive, we have decided to take a very close look at small hammock networks. That is why we have calculated exactly the reliability polynomials of small hammock networks. As far as we know, the non-trivial reliability polynomials are reported here for the first time ever. The coefficients of the reliability polynomials have been determined using our own program, and knowing all of them exactly is intended for practicality (as hammock networks might play a central role in array-based designs). The paper ends with conclusions and future directions of research.
{"title":"On hammock networks - sixty years after","authors":"S. Cowell, L. Dăuş, Valeriu Beiu, P. Poulin","doi":"10.1109/DTIS.2017.7929871","DOIUrl":"https://doi.org/10.1109/DTIS.2017.7929871","url":null,"abstract":"This paper considers the hammock networks introduced by Moore and Shannon in 1956. We mention reliability polynomials (including some of their properties) and go briefly over the state-of-the-art: theoretical, algorithmic and design oriented. These are advocating for using (small) hammock networks as a perfect fit for array-based designs of nano-devices (like, e.g., FinFETs, SegFETs, VFETs, VeSFETs, and various nanotubes transistors). Because array-based designs are expected to thrive, we have decided to take a very close look at small hammock networks. That is why we have calculated exactly the reliability polynomials of small hammock networks. As far as we know, the non-trivial reliability polynomials are reported here for the first time ever. The coefficients of the reliability polynomials have been determined using our own program, and knowing all of them exactly is intended for practicality (as hammock networks might play a central role in array-based designs). The paper ends with conclusions and future directions of research.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132858476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-04-04DOI: 10.1109/DTIS.2017.7930156
Giuseppe Airò Farulla, P. Prinetto, A. Varriale
This paper presents a methodology to implement holistic security systems on complex hardware and software platforms by means of a set of software APIs and conceptual abstraction layers which simplify both the security development and the security integration in existing infrastructures. To validate the methodology, all the hardware and software developments have been deployed on the SEcube™, an open security platform leveraging on a 3D SiP (System in Package) designed and produced by Blu5 Group, which integrates three key security elements in a single package: a fast floating-point Cortex-M4 CPU, a high-performance FPGA, and an EAL5+ certified Smart Card.
{"title":"Holistic security via complex HW/SW platforms","authors":"Giuseppe Airò Farulla, P. Prinetto, A. Varriale","doi":"10.1109/DTIS.2017.7930156","DOIUrl":"https://doi.org/10.1109/DTIS.2017.7930156","url":null,"abstract":"This paper presents a methodology to implement holistic security systems on complex hardware and software platforms by means of a set of software APIs and conceptual abstraction layers which simplify both the security development and the security integration in existing infrastructures. To validate the methodology, all the hardware and software developments have been deployed on the SEcube™, an open security platform leveraging on a 3D SiP (System in Package) designed and produced by Blu5 Group, which integrates three key security elements in a single package: a fast floating-point Cortex-M4 CPU, a high-performance FPGA, and an EAL5+ certified Smart Card.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124149426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-04-04DOI: 10.1109/dtis.2017.7930168
Ashalatha Kunnappilly, Axel Legay, T. Margaria, C. Seceleanu, B. Steffen, Louis-Marie Traonouez
Typical AAL solutions rely on integrating capabilities for health monitoring, fall detection, communication and social inclusion, supervised physical exercises, vocal interfaces, robotic platforms etc. Ensuring the safe function and quality of service with respect to various extra-functional requirements like timing and security of such AAL solutions is of highest importance. To facilitate analysis, latest system development platforms provide underlying infrastructures for model-driven design (e.g., via the DIME tool), timing and resource-usage specification (e.g., via the REMES tool), security features (e.g., by employing SECube), and statistical model-checking techniques (e.g, via Plasma). In this paper, we discuss the challenges associated with analyzing complex AAL solutions, from relevant properties to semantic interoperability issues raised by employing various frameworks for modeling and analysis, and applicability to evolving architectures. We take as examples two of the prominent existing AAL architectures and our own prior experience.
{"title":"Analyzing ambient assisted living solutions: A research perspective","authors":"Ashalatha Kunnappilly, Axel Legay, T. Margaria, C. Seceleanu, B. Steffen, Louis-Marie Traonouez","doi":"10.1109/dtis.2017.7930168","DOIUrl":"https://doi.org/10.1109/dtis.2017.7930168","url":null,"abstract":"Typical AAL solutions rely on integrating capabilities for health monitoring, fall detection, communication and social inclusion, supervised physical exercises, vocal interfaces, robotic platforms etc. Ensuring the safe function and quality of service with respect to various extra-functional requirements like timing and security of such AAL solutions is of highest importance. To facilitate analysis, latest system development platforms provide underlying infrastructures for model-driven design (e.g., via the DIME tool), timing and resource-usage specification (e.g., via the REMES tool), security features (e.g., by employing SECube), and statistical model-checking techniques (e.g, via Plasma). In this paper, we discuss the challenges associated with analyzing complex AAL solutions, from relevant properties to semantic interoperability issues raised by employing various frameworks for modeling and analysis, and applicability to evolving architectures. We take as examples two of the prominent existing AAL architectures and our own prior experience.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114373622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-04-04DOI: 10.1109/DTIS.2017.7930166
R. B. Fraj, V. Beroulle, N. Fourty, A. Meddeb
Radio Frequency Identification (RFID) devices are widely used in many domains such as tracking, marking and management of goods, smart houses (IoT), supply chains, etc. However, there is a big number of challenges which must still be overcome to ensure RFID security and privacy. In addition, due to the low cost and low consumption power of UHF RFID tags, communications between tags and readers are not robust. In this paper, we present our approach to evaluate at the same time the security and the safety of UHF RFID systems in order to improve them. First, this approach allows validating UHF RFID systems by simulation of the system behavior in presence of faults in a real environment. Secondly, evaluating the system robustness and the security of the used protocols, this approach will enable us to propose the development of new more reliable and secure protocols. Finally, it leads us to develop and validate new low cost and secure tag hardware architectures.
{"title":"A global approach for the improvement of UHF RFID safety and security","authors":"R. B. Fraj, V. Beroulle, N. Fourty, A. Meddeb","doi":"10.1109/DTIS.2017.7930166","DOIUrl":"https://doi.org/10.1109/DTIS.2017.7930166","url":null,"abstract":"Radio Frequency Identification (RFID) devices are widely used in many domains such as tracking, marking and management of goods, smart houses (IoT), supply chains, etc. However, there is a big number of challenges which must still be overcome to ensure RFID security and privacy. In addition, due to the low cost and low consumption power of UHF RFID tags, communications between tags and readers are not robust. In this paper, we present our approach to evaluate at the same time the security and the safety of UHF RFID systems in order to improve them. First, this approach allows validating UHF RFID systems by simulation of the system behavior in presence of faults in a real environment. Secondly, evaluating the system robustness and the security of the used protocols, this approach will enable us to propose the development of new more reliable and secure protocols. Finally, it leads us to develop and validate new low cost and secure tag hardware architectures.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124842522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-04-04DOI: 10.1109/DTIS.2017.7929872
Hoang Anh Du Nguyen, Lei Xie, Jintao Yu, M. Taouil, S. Hamdioui
Today's computing systems suffer from a memory/communication bottleneck, resulting in high energy consumption and saturated performance. This makes them inefficient in solving data-intensive applications at reasonable cost. Computation-In-Memory (CIM) architecture, based on the integration of storage and computation in the same physical location using non-volatile memristor crossbar technology, offers a potential solution to the memory bottleneck. An efficient interconnect network is essential to maximize CIM's architectural performance. This paper presents three interconnect network schemes for CIM architecture; these are (1) CMOS-based, (2) memristor-based and (3) hybrid cmos/memristor interconnect network scheme. To illustrate the feasibility of such schemes, a CIM parallel adder is used as a case study. The results show that the hybrid interconnect network scheme achieves a higher performance in comparison with the CMOS-based and memristor-based interconnect scheme in terms of delay, energy and area.
{"title":"Interconnect networks for resistive computing architectures","authors":"Hoang Anh Du Nguyen, Lei Xie, Jintao Yu, M. Taouil, S. Hamdioui","doi":"10.1109/DTIS.2017.7929872","DOIUrl":"https://doi.org/10.1109/DTIS.2017.7929872","url":null,"abstract":"Today's computing systems suffer from a memory/communication bottleneck, resulting in high energy consumption and saturated performance. This makes them inefficient in solving data-intensive applications at reasonable cost. Computation-In-Memory (CIM) architecture, based on the integration of storage and computation in the same physical location using non-volatile memristor crossbar technology, offers a potential solution to the memory bottleneck. An efficient interconnect network is essential to maximize CIM's architectural performance. This paper presents three interconnect network schemes for CIM architecture; these are (1) CMOS-based, (2) memristor-based and (3) hybrid cmos/memristor interconnect network scheme. To illustrate the feasibility of such schemes, a CIM parallel adder is used as a case study. The results show that the hybrid interconnect network scheme achieves a higher performance in comparison with the CMOS-based and memristor-based interconnect scheme in terms of delay, energy and area.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128930810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-04-04DOI: 10.1109/DTIS.2017.7930172
G. Harcha, A. Bosio, P. Girard, A. Virazel, P. Bernardi
Embedded SRAM elements are becoming the main detractor of the overall System-on-Chip (SoC) yield. To increase the reliability of embedded SRAMs, the use of Error Correction Code (ECC) has been widely adopted. Depending on the implemented ECC scheme, SRAMs can detect/correct the presence of one or more transient errors during the mission time. In this paper, we investigate the possibility of exploiting the ECC for dealing with permanent faults due to physical defects in embedded SRAM. In this work, we present an effective fault-injection framework to inject static and dynamic faults and to determine their impact on a given ECC scheme. As case study, the target memory is a word-oriented SRAM including detection and correction codes. The proposed framework makes possible the evaluation of the SRAM behavior in the presence of different faulty scenarios. Injected faults involve single as well as multiple cells with static and dynamic behaviors.
{"title":"An effective fault-injection framework for memory reliability enhancement perspectives","authors":"G. Harcha, A. Bosio, P. Girard, A. Virazel, P. Bernardi","doi":"10.1109/DTIS.2017.7930172","DOIUrl":"https://doi.org/10.1109/DTIS.2017.7930172","url":null,"abstract":"Embedded SRAM elements are becoming the main detractor of the overall System-on-Chip (SoC) yield. To increase the reliability of embedded SRAMs, the use of Error Correction Code (ECC) has been widely adopted. Depending on the implemented ECC scheme, SRAMs can detect/correct the presence of one or more transient errors during the mission time. In this paper, we investigate the possibility of exploiting the ECC for dealing with permanent faults due to physical defects in embedded SRAM. In this work, we present an effective fault-injection framework to inject static and dynamic faults and to determine their impact on a given ECC scheme. As case study, the target memory is a word-oriented SRAM including detection and correction codes. The proposed framework makes possible the evaluation of the SRAM behavior in the presence of different faulty scenarios. Injected faults involve single as well as multiple cells with static and dynamic behaviors.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132422498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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