K. Sagara, T. Kure, S. Shukuri, J. Yugami, N. Hasegawa, H. Shinriki, H. Goto, H. Yamashita, E. Takeda
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引用次数: 8
Abstract
A recessed stacked capacitor (RSTC) structure to achieve both fine-pattern delineation and high cell capacitance is presented. Using a RSTC structure, an experimental memory array with 0.25 mu m phase-shift lithography and CVD-W plate technology has been fabricated. A 25-fF/cell capacitance was obtained in a 0.72 mu m/sup 2/ cell.<>
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