Kohei Oasa, T. Nishiwaki, T. Ohguro, Yasunobu Saito, Y. Kawaguchi
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Abstract
To accelerate the development of low voltage MOSFET, we designed a test element group pattern that enables on-resistance measurement at wafer level. We confirmed that the on-resistance can be measured at wafer level by optimizing the device size and contact method to eliminate the influence of parasitic resistance.
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