Simulating DDR5 Systems with Clocked Receivers

Abstract

The inclusion of a receiver decision feedback equalizer (DFE) to Double Data Rate 5(DDRS) synchronous dynamic random access memory (SDRAM)s has increased the complexity of signal integrity (SI) simulation compared to previous DDR technologies. In response, the I/O Buffer Information Specification (IBIS) version 7.1 enables an IBIS algorithmic modeling interface (IBIS-AMI) receiver model to accept an external clock signal. A novel simulation flow is developed which accounts for both DQ (data) signals and their associated DQS (clock/strobe) signal in the evaluation of DDR5 data write and read operations. The effects of including DQS into SI simulation of DDR5 systems are discussed by examining the resulting eye diagrams. It is observed that for system timing margins, the SI quality of the strobe signal becomes just as important as the data signals.