K. Fukasaku, Daisuke Nakagawa, Toshihiko Miyazaki, T. Tatsumi, H. Ohnuma
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引用次数: 1
Abstract
Our new ESD design methodology use gate work function control and channel length optimization. We developed a P/N hybrid gate NMOS, where P gate in the channel region reduces subthreshold leakage current thanks to a higher Vth, and N gate in the overlap region reduces GIDL thanks to a lower electric field.
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