{"title":"A reconfigurable WSI neural network","authors":"F. Blayo, P. Hurat","doi":"10.1109/WAFER.1989.47545","DOIUrl":null,"url":null,"abstract":"The solution presented consists of implementing the N neuron Hopfield network as a systolic square array made up of N/sup 2/ cells. Systolic arrays are well suited to wafer-scale integration (WSI). Inherent error tolerance of neural networks facilitates wafer design. However, a wafer-level reconfiguration is required to bypass faulty chips. The principle and the architecture of a switching element which provides a flexible wafer-level reconfiguration is described.<<ETX>>","PeriodicalId":412685,"journal":{"name":"[1989] Proceedings International Conference on Wafer Scale Integration","volume":"52 12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1989] Proceedings International Conference on Wafer Scale Integration","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/WAFER.1989.47545","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
The solution presented consists of implementing the N neuron Hopfield network as a systolic square array made up of N/sup 2/ cells. Systolic arrays are well suited to wafer-scale integration (WSI). Inherent error tolerance of neural networks facilitates wafer design. However, a wafer-level reconfiguration is required to bypass faulty chips. The principle and the architecture of a switching element which provides a flexible wafer-level reconfiguration is described.<>
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