Latch clustering for minimizing detection-to-boosting latency toward low-power resilient circuits

Abstract

Dynamic voltage scaling (DVS) has become one of the most effective approaches to achieve ultra-low-power SoC. To eliminate timing errors arising from DVS, several error-resilient circuit design techniques were proposed to detect and/or correct timing violations. The most recently proposed time-borrowing-and-local-boosting (TBLB) technique has the advantage of lower power consumption and less performance degradation due to the needlessness of pipeline stalls. On the other hand, to make the best use of the TBLB technique, a special timing requirement for TBLB latches must be considered in the physical design process. To address this issue, a novel reliability-aware latch clustering method for low-power TBLB resilient circuits is introduced. Experimental results show that the proposed approach is very effective in reducing the delay of both combinational and error-detection circuits, which indicates better circuit reliability.