G. J. Hu, L. Tran, P. Keshtbod, J. Segal, K. Park, T. Amin, B. Prickett, S.C. Tsao, J. Yen, E. Smith, J. Bornstein, A. Alvarez
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引用次数: 0
Abstract
An advanced BiCMOS floating gate avalanche MOS (BiFAMOS) technology for high-speed and high-density EPROM applications is described. It is of great interest to develop chips with access times of 20 ns or less to support 33-to-50-MHz systems without a SRAM interface. Since channel hot carrier injection is used in EPROM programming, the high-current and high-voltage programming conditions limit the size of the FET that can be used in the cell and hence the low cell current directly affects speed. A two-transistor cell has been previously introduced to overcome this speed limitation but at the expense of area. Here, BiCMOS technology is used to alleviate this speed/area tradeoff. Fast bipolar sense amplifiers and high-current NPN drivers allow very-high-speed access without a large cell current. With a 1-T cell, an access time of 12 ns was obtained on a 1-Mb EPROM, demonstrating that this 0.8- mu m BiFAMOS is capable of sub-20-ns 4M EPROMs.<>
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