Low-power high-speed 1-V LSI using a 0.25-/spl mu/m MTCMOS/SIMOX technique

S. Shigematsu, T. Hatano, Y. Tanabe, S. Mutoh
{"title":"Low-power high-speed 1-V LSI using a 0.25-/spl mu/m MTCMOS/SIMOX technique","authors":"S. Shigematsu, T. Hatano, Y. Tanabe, S. Mutoh","doi":"10.1109/ASIC.1998.722812","DOIUrl":null,"url":null,"abstract":"A 1-V low-power high-speed circuit technique has been developed using a multi-threshold CMOS (MTCMOS) scheme with separation by implanted oxygen (SIMOX) SOI technology. The combination of MTCMOS and SIMOX results in 60%-faster operation and 80%-lower power consumption, compared to a conventional CMOS/bulk circuit. In order to reduce the power of not only the circuit but also the system, we propose an interface scheme that is compatible with conventional LSIs or transfers signal at high speed and low power. A standard-cell-based MPU was fabricated using 0.25-/spl mu/m MTCMOS/SIMOX. The maximum operating frequency is over 100 MHz and the energy consumption is 0.5 mW/MHz at the supply voltage of 1.0 V.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1998.722812","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

A 1-V low-power high-speed circuit technique has been developed using a multi-threshold CMOS (MTCMOS) scheme with separation by implanted oxygen (SIMOX) SOI technology. The combination of MTCMOS and SIMOX results in 60%-faster operation and 80%-lower power consumption, compared to a conventional CMOS/bulk circuit. In order to reduce the power of not only the circuit but also the system, we propose an interface scheme that is compatible with conventional LSIs or transfers signal at high speed and low power. A standard-cell-based MPU was fabricated using 0.25-/spl mu/m MTCMOS/SIMOX. The maximum operating frequency is over 100 MHz and the energy consumption is 0.5 mW/MHz at the supply voltage of 1.0 V.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
采用0.25-/spl mu/m MTCMOS/SIMOX技术的低功耗高速1-V LSI
采用植入氧(SIMOX) SOI技术分离的多阈值CMOS (MTCMOS)方案,开发了一种1v低功耗高速电路技术。与传统的CMOS/体电路相比,MTCMOS和SIMOX的结合可使运行速度提高60%,功耗降低80%。为了降低电路和系统的功耗,我们提出了一种兼容传统lsi或高速低功耗传输信号的接口方案。采用0.25-/spl μ m MTCMOS/SIMOX制备了基于标准单元的微处理器。电源电压为1.0 V时,最大工作频率大于100mhz,能耗为0.5 mW/MHz。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Relaxed partitioning balance constraints in top-down placement Design and test of a CMOS low-power mixed-analog/digital ASIC for radiation detector readout front ends Substrate noise in mixed signal circuits: two case studies [CMOS] 800 K gates of random logic in four months: discussion on design methodologies based on "IDEFIX" ASIC experience Methodology for process portable hard IP block creation using cell based array architecture
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1