Critical Charge Dependency of Single Event Upset (SEU) on the Supply Voltage in Nanometric CMOS SRAMs

Abstract

Rapid scaling of integrated devices and circuits has been led to the serious concerns in nanometric technologies. Continuous downscaling of CMOS technology has been resulted into the decrease in the critical charge of memory devices like SRAM in nanometric technologies and made them more susceptible to Single Event Upsets (SEUs). Critical charge as the criterion of SEU vulnerability, is the minimum charge required to change a memory cell which is mainly attributed to the scaling of the supply voltage. In this paper, the dependence of critical charge on the supply voltage in a 65-nm CMOS SRAM has been studied. To this purpose, a memory cell was designed using Silvaco TCAD tool and incident particles with different values of Linear Energy Transfer (LET) struck on it. Then, the critical charge has been calculated at three supply voltages. The results exhibit significant changes of critical charge due to supply voltage variations. So that, lowering in the supply voltage has been resulted to the decrease in critical charge.