Interposers for power supply voltage noise reduction

Abstract

This report proposes low power supply noise interposers with two types of structures based on embedding technologies. These structures reduce (i) self-noise and (ii) transfer-noise. We designed and developed these two structures and evaluated them experimentally. Using small chip components (0402) permitted interposer heights of less than 0.6 mm. The measurement results indicate the following: (i) reductions of on-chip power supply noise on the order of several hundreds of MHz; (ii) S21 less than -60dB achieved from 10 MHz to a few GHz.