Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457893
Biancun Xie, Madhavan Swaminathan
In this paper, an efficient hybrid modeling approach for power delivery network (PDN) with through-silicon vias (TSVs) for 3D systems is proposed. The proposed approach extends multi-layer finite difference method (M-FDM) to include TSVs by extracting their parasitic behavior using an integral equation based solver. Using the proposed modeling technique the power/signal integrity of PDN with TSVs/through-glass vias (TGVs) in lossy silicon interposer and low loss glass interposer is investigated and compared. The comparison indicates the benefits of using silicon interposer for high speed signaling.
{"title":"Modeling and analysis of SSN in silicon and glass interposers for 3D systems","authors":"Biancun Xie, Madhavan Swaminathan","doi":"10.1109/EPEPS.2012.6457893","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457893","url":null,"abstract":"In this paper, an efficient hybrid modeling approach for power delivery network (PDN) with through-silicon vias (TSVs) for 3D systems is proposed. The proposed approach extends multi-layer finite difference method (M-FDM) to include TSVs by extracting their parasitic behavior using an integral equation based solver. Using the proposed modeling technique the power/signal integrity of PDN with TSVs/through-glass vias (TGVs) in lossy silicon interposer and low loss glass interposer is investigated and compared. The comparison indicates the benefits of using silicon interposer for high speed signaling.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"16 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120856095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457860
Shih-Ya Huang, Yung-Shou Cheng, Bob Liu, R. Wu
A simple formula is derived to estimate the worst-case eye height for mismatched transmission line systems, using system pulse response and the idea of peak distortion analysis. A contour map which represents eye height variations for different reflection coefficients at the drivers and receivers is constructed and used to facilitate the driver and termination designs for the best eye diagram performance. Subsequently, the eye diagram results for two different mismatched transmission lines are given to validate the accuracy of the presented contour map.
{"title":"Enhanced eye-height estimation of mismatched lossy transmission lines","authors":"Shih-Ya Huang, Yung-Shou Cheng, Bob Liu, R. Wu","doi":"10.1109/EPEPS.2012.6457860","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457860","url":null,"abstract":"A simple formula is derived to estimate the worst-case eye height for mismatched transmission line systems, using system pulse response and the idea of peak distortion analysis. A contour map which represents eye height variations for different reflection coefficients at the drivers and receivers is constructed and used to facilitate the driver and termination designs for the best eye diagram performance. Subsequently, the eye diagram results for two different mismatched transmission lines are given to validate the accuracy of the presented contour map.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125904263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457862
Kiyeong Kim, Kyoungchoul Koo, Seulki Hong, Jonghoon J. Kim, Byung-Ho Cho, Joungho Kim
Vertical noise coupling caused by the near-field coupling between the RF/analog IC and logic IC is a severe problem in 3D mixed-signal systems. To reduce the vertical noise coupling, graphene is an appropriate material due to its inherent characteristics such as very low thickness, high flexibility, high mechanical strength, and EMI absorbing characteristic. Especially, the EMI absorbing characteristic is an important property as the shield to prevent the vertical noise coupling, as it reduces the re-coupling of the reflected EMI by the shield into other ICs. We measure the reduction of the vertical noise coupling by the mono-layer graphene shield in the 3D mixed-signal system composed of a low noise amplifier (LNA), an on-chip switching model DC-DC converter, and the mono-layer graphene in the frequency and time domain. Through the measurement results, we observed that the mono-layer graphene can maximally reduce the vertical noise coupling by -17 dB in the frequency domain. Additionally, the vertically coupled noise is reduced by 25% in the time domain measurement.
{"title":"Graphene-based EMI shielding for vertical noise coupling reduction in 3D mixed-signal system","authors":"Kiyeong Kim, Kyoungchoul Koo, Seulki Hong, Jonghoon J. Kim, Byung-Ho Cho, Joungho Kim","doi":"10.1109/EPEPS.2012.6457862","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457862","url":null,"abstract":"Vertical noise coupling caused by the near-field coupling between the RF/analog IC and logic IC is a severe problem in 3D mixed-signal systems. To reduce the vertical noise coupling, graphene is an appropriate material due to its inherent characteristics such as very low thickness, high flexibility, high mechanical strength, and EMI absorbing characteristic. Especially, the EMI absorbing characteristic is an important property as the shield to prevent the vertical noise coupling, as it reduces the re-coupling of the reflected EMI by the shield into other ICs. We measure the reduction of the vertical noise coupling by the mono-layer graphene shield in the 3D mixed-signal system composed of a low noise amplifier (LNA), an on-chip switching model DC-DC converter, and the mono-layer graphene in the frequency and time domain. Through the measurement results, we observed that the mono-layer graphene can maximally reduce the vertical noise coupling by -17 dB in the frequency domain. Additionally, the vertically coupled noise is reduced by 25% in the time domain measurement.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116162968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457863
Z. Tong, A. Fischer, A. Stelzer, L. Maurer
This paper presents an antenna in package (AiP) solution with embedded wafer level ball grid array (eWLB) packaging technology. The antenna implements superstrate structure configuration. A cavity in the PCB is introduced below the antenna area is introduced to increase the distance between antenna and ground on the PCB. This extends the relative bandwidth of the AiP by up to 36% for 10 dB return loss. Further, a hemisphere dielectric lens was also designed to improve the radiation performance of the AiP. Measurements show that the dielectric lens optimizes the radiation pattern of the AiP and increases the TX equivalent isotropic radiated power (EIRP) of the package from 9.0 dBm to 13.5 dBm at 76 GHz. This concept is suitable for a wide area of millimeter-wave front-end applications. The 3-dB beamwidths in the E- and H-planes of the package with lens were measured to be 38° and 53° respectively.
{"title":"Bandwidth and gain enhancement of antenna in package","authors":"Z. Tong, A. Fischer, A. Stelzer, L. Maurer","doi":"10.1109/EPEPS.2012.6457863","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457863","url":null,"abstract":"This paper presents an antenna in package (AiP) solution with embedded wafer level ball grid array (eWLB) packaging technology. The antenna implements superstrate structure configuration. A cavity in the PCB is introduced below the antenna area is introduced to increase the distance between antenna and ground on the PCB. This extends the relative bandwidth of the AiP by up to 36% for 10 dB return loss. Further, a hemisphere dielectric lens was also designed to improve the radiation performance of the AiP. Measurements show that the dielectric lens optimizes the radiation pattern of the AiP and increases the TX equivalent isotropic radiated power (EIRP) of the package from 9.0 dBm to 13.5 dBm at 76 GHz. This concept is suitable for a wide area of millimeter-wave front-end applications. The 3-dB beamwidths in the E- and H-planes of the package with lens were measured to be 38° and 53° respectively.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122525242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457856
M. Farhan, E. Gad, M. Nakhla, R. Achar
This paper presents a new method for a circuit-based transient simulation of large interconnects circuits terminated with nonlinear devices. The proposed method is based on high-order A-stable integration methods, known as Obreshkov-formula. The new method exploits the structure of the matrices resulting from applying Obreshkov-formula to achieve very high speedups. A numerical example is presented that shows the performance and accuracy of the proposed method.
{"title":"An efficient method for transient simulation of high-speed interconnects with nonlinear terminations","authors":"M. Farhan, E. Gad, M. Nakhla, R. Achar","doi":"10.1109/EPEPS.2012.6457856","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457856","url":null,"abstract":"This paper presents a new method for a circuit-based transient simulation of large interconnects circuits terminated with nonlinear devices. The proposed method is based on high-order A-stable integration methods, known as Obreshkov-formula. The new method exploits the structure of the matrices resulting from applying Obreshkov-formula to achieve very high speedups. A numerical example is presented that shows the performance and accuracy of the proposed method.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123608367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457913
T. Mido, R. Kobayashi, G. Kubo, H. Otsuka, Y. Kobayashi, H. Fujii, T. Sudo
Power integrity is a serious issue in the modern CMOS digital systems, because power supply noise excited in core circuits induces logic instability and electromagnetic radiation. Therefore, chip-package co-design is becoming important by taking into consideration the total impedance of power distribution network (PDN) seen from the chip. Especially, parallel resonance peaks in the PDN due to the chip-package interaction induces the unwanted power supply fluctuation, and results in the degradation of signal integrity and electromagnetic interference (EMI). In this paper, effects of critical damping condition for the total PDN impedance on power supply noise has been studied by adding different RC circuit to the intrinsic on-die RC circuit of chip. Three test chips were assumed to be designed with different on-chip PDN properties. The simulated power supply noises for the three test chips showed typical characteristics of oscillatory region and damped regions The critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on the chip.
{"title":"Chip-package co-design for suppressing parallel resonance and power supply noise","authors":"T. Mido, R. Kobayashi, G. Kubo, H. Otsuka, Y. Kobayashi, H. Fujii, T. Sudo","doi":"10.1109/EPEPS.2012.6457913","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457913","url":null,"abstract":"Power integrity is a serious issue in the modern CMOS digital systems, because power supply noise excited in core circuits induces logic instability and electromagnetic radiation. Therefore, chip-package co-design is becoming important by taking into consideration the total impedance of power distribution network (PDN) seen from the chip. Especially, parallel resonance peaks in the PDN due to the chip-package interaction induces the unwanted power supply fluctuation, and results in the degradation of signal integrity and electromagnetic interference (EMI). In this paper, effects of critical damping condition for the total PDN impedance on power supply noise has been studied by adding different RC circuit to the intrinsic on-die RC circuit of chip. Three test chips were assumed to be designed with different on-chip PDN properties. The simulated power supply noises for the three test chips showed typical characteristics of oscillatory region and damped regions The critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on the chip.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116201039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457912
S. Aroor, R. Pierce, R. Henderson, A. Blanchard
This paper demonstrates coplanar waveguide (CPW) interconnects and radiators for antenna-in-package (AiP) solutions at millimeter-wave frequencies using flame-resistant 4 (FR-4) laminates. CPW transmission lines and broadband antennas with CPW feeds have been fabricated on two types of FR-4 laminates to detail the performance of this material. Measurements show an average attenuation of 0.19 dB/mm at 60 GHz, which is comparable to that of other packaging substrates at millimeter wavelengths. CPW-fed bow-tie apertures have a return loss below 10 dB from 60 GHz to 90 GHz.
{"title":"Millimeter-wave coplanar interconnects and radiators on FR-4 laminates","authors":"S. Aroor, R. Pierce, R. Henderson, A. Blanchard","doi":"10.1109/EPEPS.2012.6457912","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457912","url":null,"abstract":"This paper demonstrates coplanar waveguide (CPW) interconnects and radiators for antenna-in-package (AiP) solutions at millimeter-wave frequencies using flame-resistant 4 (FR-4) laminates. CPW transmission lines and broadband antennas with CPW feeds have been fabricated on two types of FR-4 laminates to detail the performance of this material. Measurements show an average attenuation of 0.19 dB/mm at 60 GHz, which is comparable to that of other packaging substrates at millimeter wavelengths. CPW-fed bow-tie apertures have a return loss below 10 dB from 60 GHz to 90 GHz.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124339435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457908
M. Mehri, R. Sarvari, A. Seydolhosseini
In this paper, jitter due to both capacitive and inductive coupling is studied. Maximum frequency of driving signal on a wire is limited by its input rise time, fall time, pulse width, and the coupling effect from its neighbors. The analytical expressions to estimate the deterministic jitter time due to these effects are presented. The estimation is based on the fastest and slowest approximation of the signal waveform components. Also, we have extracted the eye opening parameters of the eye diagram. The inductance effects significance is shown on eye opening and jitter time. The 45nm technology is used for estimating the horizontal and vertical eye opening and jitter time. The presented formula is compared with the simulations for some cases and it shows good agreements.
{"title":"Eye diagram parameter extraction of nano scale VLSI interconnects","authors":"M. Mehri, R. Sarvari, A. Seydolhosseini","doi":"10.1109/EPEPS.2012.6457908","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457908","url":null,"abstract":"In this paper, jitter due to both capacitive and inductive coupling is studied. Maximum frequency of driving signal on a wire is limited by its input rise time, fall time, pulse width, and the coupling effect from its neighbors. The analytical expressions to estimate the deterministic jitter time due to these effects are presented. The estimation is based on the fastest and slowest approximation of the signal waveform components. Also, we have extracted the eye opening parameters of the eye diagram. The inductance effects significance is shown on eye opening and jitter time. The 45nm technology is used for estimating the horizontal and vertical eye opening and jitter time. The presented formula is compared with the simulations for some cases and it shows good agreements.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126245569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457845
Joon Hyung Chung, A. Cangellaris
A methodology is proposed for the fast assessment of the impact of electromagnetic loading by surrounding wiring on the signal transmission properties of a high-speed interconnect channel. The proposed methodology is aimed at alleviating the computational complexity of the electromagnetic modeling of the channel including the details of the wiring in its surrounding that, more often than not and especially in the early stages of design, are not well defined and thus are best accounted for through a Monte Carlo analysis. Instead, use of a stochastic macromodel for the channel is proposed that incorporates the electromagnetic attributes of the surrounding wiring through a statistical description of its loading on the interconnects of the channel. The proposed method makes use of parametric rational interpolation to develop a frequency-dependent macromodel that is valid over the multi-dimensional space that describes the uncertainty of the neighboring layout topography. Making use of stochastic collocation, the channel macromodel lends itself to fast quantitative analysis of the channel transmission properties and signal degradation in both frequency and time domain. A simple channel example, which allows us to assess the accuracy of the proposed method, is used to demonstrate the key attributes of the proposed method and comment on its usefulness as a computer-aided tool for noise-aware wiring layout planning.
{"title":"Fast assessment of the impact of surrounding wiring on the transmission properties of high-speed interconnect channels","authors":"Joon Hyung Chung, A. Cangellaris","doi":"10.1109/EPEPS.2012.6457845","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457845","url":null,"abstract":"A methodology is proposed for the fast assessment of the impact of electromagnetic loading by surrounding wiring on the signal transmission properties of a high-speed interconnect channel. The proposed methodology is aimed at alleviating the computational complexity of the electromagnetic modeling of the channel including the details of the wiring in its surrounding that, more often than not and especially in the early stages of design, are not well defined and thus are best accounted for through a Monte Carlo analysis. Instead, use of a stochastic macromodel for the channel is proposed that incorporates the electromagnetic attributes of the surrounding wiring through a statistical description of its loading on the interconnects of the channel. The proposed method makes use of parametric rational interpolation to develop a frequency-dependent macromodel that is valid over the multi-dimensional space that describes the uncertainty of the neighboring layout topography. Making use of stochastic collocation, the channel macromodel lends itself to fast quantitative analysis of the channel transmission properties and signal degradation in both frequency and time domain. A simple channel example, which allows us to assess the accuracy of the proposed method, is used to demonstrate the key attributes of the proposed method and comment on its usefulness as a computer-aided tool for noise-aware wiring layout planning.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124623201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/EPEPS.2012.6457839
H. Lan, Minghui Han, R. Schmitt
Analyzing power supply noise characteristics and predicting its jitter impact is critical in designing the 12.8Gbps single-ended memory interface achieving better than 5mW/Gbps energy efficiency. The clocking circuit jitter performance is characterized by jitter sensitivity. The power supply noise induced jitter (PSIJ) is derived by combining the noise spectrum and sensitivity profile. The final PSIJ prediction matches closely with the on-chip measurement result.
{"title":"Modeling and measurement of supply noise induced jitter in a 12.8Gbps single-ended memory interface","authors":"H. Lan, Minghui Han, R. Schmitt","doi":"10.1109/EPEPS.2012.6457839","DOIUrl":"https://doi.org/10.1109/EPEPS.2012.6457839","url":null,"abstract":"Analyzing power supply noise characteristics and predicting its jitter impact is critical in designing the 12.8Gbps single-ended memory interface achieving better than 5mW/Gbps energy efficiency. The clocking circuit jitter performance is characterized by jitter sensitivity. The power supply noise induced jitter (PSIJ) is derived by combining the noise spectrum and sensitivity profile. The final PSIJ prediction matches closely with the on-chip measurement result.","PeriodicalId":188377,"journal":{"name":"2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129615328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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