Estimation of average energy consumption of ripple-carry adder based on average length carry chains

VLSI Signal Processing, IX Pub Date : 1996-10-30 DOI:10.1109/VLSISP.1996.558326

K. Parhi, Janardhan H. SatyanarayanaDepartment

引用次数: 21

Abstract

We show theoretically that the average energy consumption of a ripple-carry adder is O(W), and the upper bound on the average energy consumption is O(Wlog/sub 2/W), where W is the word-length of the operands. Our theoretical analysis is based on a simple state transition diagram (STD) model of a full adder cell and the observations that the average length of a carry propagation chain is v=2, and the average length of the maximum carry chain is v/spl les/log/sub 2/W. To verify our theoretical conclusions, we use the HEAT CAD tool to estimate the average power consumed by the ripple-carry adder for word-lengths 4/spl les/W/spl les/64. The experimental results show that, for W/spl ges/16, the error in our theoretical estimations is around 15%.

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基于平均进位链长度的纹波进位加法器平均能耗估算

我们从理论上证明了纹波进位加法器的平均能量消耗为O(W)，平均能量消耗的上界为O(Wlog/sub 2/W)，其中W为操作数的字长。我们的理论分析基于一个完整加法器单元的简单状态转移图(STD)模型，并观察到进位传播链的平均长度为v=2，最大进位传播链的平均长度为v/spl les/log/sub 2/W。为了验证我们的理论结论，我们使用HEAT CAD工具来估计字长为4/spl les/W/spl les/64的纹波进位加法器的平均功耗。实验结果表明，对于W/spl /16，我们的理论估计误差在15%左右。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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VLSI Signal Processing, IX

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