Design and Analysis of MOSFET Based on Fan-out Panel-Level Package Technology

Abstract

Nowadays, fan-out package has received extensive attention from enterprises and researchers because it possesses lower cost, smaller size, higher packaging efficiency, and better electrical and thermal performance. As one of the fan-out packages, panel-level fan-out package has advantages in single package cost, board utilization, and packaging efficiency. In this paper, based on the panel-level fan-out package process, a power MOSFET device is designed, which is composed of pads, solder, chip, circuits and molding compound. The drain of the chip is fixed on the copper pad by solder, and the gate and source are interconnected with the pads through laser drilling and electroplating processes. Finally, realize the electrical connection of the chip. In addition, the thermal resistance of the MOSFET device is analyzed by the commercial software ICEPAK. The results show that the thermal resistance of MOSFET based on fan-out panel-level package process is 43.44°C /W, which is 11.4% lower than the traditional wire-bonding process. The MOSFET based on fan-out panel-level package process has good heat dissipation performance.