An efficient Mesh-of-Tree based interconnect architecture for high performance 3D FPGAs

Abstract

In this paper we propose a three-dimensional (3D) interconnect network implementation based on a modified Mesh-of-Trees (MoT) topology for FPGA architecture design. To obtain the optimal MoT-based interconnect structure, the routing architecture of the 2D MoT-based FPGA is modified to include long routing segments that span multiple switch blocks in every row and column. By adjusting the percentage of long wire and span, a 2.5D or 3D high density MoT FPGAs can be designed. To design 3D multi-stacked MoT-based FPGAs, the 2D MoT FPGA is cut into two or more equal sections by adjusting the long wire span. The long wire segments are realized using 3D through silicon via (TSV). To design 2.5D interposer-based multi-FPGAs, we increase the number of cuts and apply appropriate optimization models to scale down the number of long wires and horizontal inter-FPGA interposer wires. Using our 2.5/3D design and simulation CAD flow, we demonstrate the speed and area of 3D MoT-based FPGA architecture is improved by 54% and 41% respectively in comparison to 3D Mesh-based FPGA.