{"title":"Performance limits of NMOS and CMOS","authors":"J. Pfiester, J. Shott, J. Meindl","doi":"10.1109/ISSCC.1984.1156715","DOIUrl":null,"url":null,"abstract":"An analytic MOST model to project circuit performance limits will be reported. Minimum channel lengths of 0.14 and 0.40μm, corresponding to logic gate delays of 19ps for CMOS and 103ps for NMOS are predicted.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"57 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1984.1156715","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
An analytic MOST model to project circuit performance limits will be reported. Minimum channel lengths of 0.14 and 0.40μm, corresponding to logic gate delays of 19ps for CMOS and 103ps for NMOS are predicted.
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