A. Adan, T. Naka, S. Kaneko, D. Urabe, K. Higashi, A. Kagisawa
{"title":"Low-voltage 0.35 /spl mu/m CMOS/SOI technology for high-performance ASIC's","authors":"A. Adan, T. Naka, S. Kaneko, D. Urabe, K. Higashi, A. Kagisawa","doi":"10.1109/CICC.1997.606659","DOIUrl":null,"url":null,"abstract":"A 0.35 /spl mu/m CMOS process for low-voltage, high-performance ASIC's, implemented on ultra-thin SOI (Shallow SIMOX) wafers, is described. Stable high speed, low-Vth transistors for low-voltage operation at 1.5v are integrated in a salicided dual-gate process. Shallow SIMOX devices dissipate 1/5 of the Bulk-Si power. A prototype PLL circuit operates at fmax of 1.6 GHz at 1.5v supply voltage, demonstrating the excellent performance of this technology.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1997.606659","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A 0.35 /spl mu/m CMOS process for low-voltage, high-performance ASIC's, implemented on ultra-thin SOI (Shallow SIMOX) wafers, is described. Stable high speed, low-Vth transistors for low-voltage operation at 1.5v are integrated in a salicided dual-gate process. Shallow SIMOX devices dissipate 1/5 of the Bulk-Si power. A prototype PLL circuit operates at fmax of 1.6 GHz at 1.5v supply voltage, demonstrating the excellent performance of this technology.
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