A mixed-signal array processor with early vision applications

Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI:10.1109/CICC.1997.606629

D. A. Martin

引用次数: 42

Abstract

A programmable analog arithmetic circuit which can perform addition, subtraction, multiplication, and division at 7 bits of resolution is presented. This circuit is used as the ALU for a mixed-signal array processor designed for early vision applications. The analog arithmetic circuit enables the processor to operate with the low power and low area of a dedicated analog circuit while retaining the flexibility of a digital processor. The processor was tested with an edge detection algorithm and a sub-pixel resolution algorithm. A 1 cm square array of the mixed-signal processor cells in 0.8 /spl mu/m CMOS with a 5 V power supply would dissipate 1 W at 420 MIPS.

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具有早期视觉应用的混合信号阵列处理器

提出了一种可编程的模拟运算电路，可实现7位分辨率的加、减、乘、除运算。该电路被用作用于早期视觉应用的混合信号阵列处理器的ALU。该模拟运算电路使处理器能够以专用模拟电路的低功耗和低面积运行，同时保留数字处理器的灵活性。采用边缘检测算法和亚像素分辨率算法对该处理器进行了测试。一个1平方厘米的混合信号处理器单元阵列，采用0.8 /spl μ l /m CMOS，采用5 V电源，在420 MIPS时功耗为1 W。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of CICC 97 - Custom Integrated Circuits Conference

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