A compact NBTI model for accurate analog integrated circuit reliability simulation

Abstract

Negative Bias Temperature Instability (NBTI) is one of the most important reliability concerns in nanometer CMOS technologies. Accurate models for aging effects such as NBTI can help a designer in determining and improving circuit lifetime. This paper proposes a comprehensible compact model for reliability simulation of analog integrated circuits. The proposed model includes all typical NBTI peculiarities such as relaxation after voltage stress reduction and dependence on time-varying stress voltage and temperature. Comprising both the recoverable and permanent NBTI components, the model also offers a significant accuracy improvement over existing models such as the popular Reaction-Diffusion model. It is therefore well suited for accurate circuit reliability analysis and failure-time prediction. Further, the model includes only 10 process-dependent parameters, enabling easy calibration. The model is validated on a 1.9nm EOT SiON CMOS process.