Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044229
K. Endo, Y. Ishikawa, T. Matsukawa, Yongxum Liu, S. Oruchi, K. Sakamoto, J. Tsukada, H. Yamauchi, M. Masahara
We have successfully fabricated FinFETs with a 25-nm-short extension of the source/drain by using atomic layer deposition of SiO2 thin films for the side-wall spacer of the gate electrode. The performance of the FinFET has been successfully improved by the reduction of the parasitic resistance.
{"title":"Atomic layer deposition of 25-nm-thin sidewall spacer for enhancement of FinFET performance","authors":"K. Endo, Y. Ishikawa, T. Matsukawa, Yongxum Liu, S. Oruchi, K. Sakamoto, J. Tsukada, H. Yamauchi, M. Masahara","doi":"10.1109/ESSDERC.2011.6044229","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044229","url":null,"abstract":"We have successfully fabricated FinFETs with a 25-nm-short extension of the source/drain by using atomic layer deposition of SiO2 thin films for the side-wall spacer of the gate electrode. The performance of the FinFET has been successfully improved by the reduction of the parasitic resistance.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125038655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044205
L. Pancheri, D. Stoppa
Two different Single-Photon Avalanche Diode (SPAD) structures in a standard 0.15-nm CMOS technology are presented. A characterization of the two detectors, having a 10-μm active-area diameter, and monolithically integrated with a passive quenching circuit and a fast comparator is presented. The two devices exhibit respectively a typical dark count rate of 230cps and 160cps, an afterpulsing probability of 2.1% and 1.3% at 30ns dead time, a Photon Detection Probability of 31% and 26 % at λ=470nm and a timing resolution of 170ps and 60ps. The adopted technology is therefore promising for the realization of SPAD-based image sensors with good overall performance.
{"title":"Low-noise single Photon Avalanche Diodes in 0.15 μm CMOS technology","authors":"L. Pancheri, D. Stoppa","doi":"10.1109/ESSDERC.2011.6044205","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044205","url":null,"abstract":"Two different Single-Photon Avalanche Diode (SPAD) structures in a standard 0.15-nm CMOS technology are presented. A characterization of the two detectors, having a 10-μm active-area diameter, and monolithically integrated with a passive quenching circuit and a fast comparator is presented. The two devices exhibit respectively a typical dark count rate of 230cps and 160cps, an afterpulsing probability of 2.1% and 1.3% at 30ns dead time, a Photon Detection Probability of 31% and 26 % at λ=470nm and a timing resolution of 170ps and 60ps. The adopted technology is therefore promising for the realization of SPAD-based image sensors with good overall performance.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125876160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044208
F. L. Conte, J. Sallese, M. Kayal
This paper presents a modeling methodology for substrate current coupling mechanisms. An equivalent schematic is made using enhanced model of resistances and diodes. These enhanced components were developed in previous work and account for minority and majority carrier propagation inside the semiconductor substrates. For the first time an equivalent schematic accounting for minority carrier is validated on an integrated circuit by modeling the current coupling occurring between two high-voltage H-bridges. The results obtained from the lumped model are in very good agreement with measurements. For the first time, a simulation methodology is proposed to accurately model substrate of smart power IC's using low computer resource.
{"title":"Predictive modeling of parasitic substrate currents in high-voltage smart power IC's","authors":"F. L. Conte, J. Sallese, M. Kayal","doi":"10.1109/ESSDERC.2011.6044208","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044208","url":null,"abstract":"This paper presents a modeling methodology for substrate current coupling mechanisms. An equivalent schematic is made using enhanced model of resistances and diodes. These enhanced components were developed in previous work and account for minority and majority carrier propagation inside the semiconductor substrates. For the first time an equivalent schematic accounting for minority carrier is validated on an integrated circuit by modeling the current coupling occurring between two high-voltage H-bridges. The results obtained from the lumped model are in very good agreement with measurements. For the first time, a simulation methodology is proposed to accurately model substrate of smart power IC's using low computer resource.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125936534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044176
Y. Joly, L. Lopez, J. Portal, H. Aziza, P. Masson, J. Ogier, Y. Bert, F. Julien, P. Fornara
Low power analog circuits needs large and short MOSFETs biased in the sub-threshold area with good performances in terms of matching. In order to reach these specifications, octagonal transistors are proposed. Due to their design, these transistors avoid hump effect. As a consequence, gate-source voltage matching under-threshold is always at its best level. Moreover, the paper shows the device robustness to hot carrier stress is improved on octagonal NMOS; VT matching degradation due to hot carrier stress is also improved with an octagonal design.
{"title":"Octagonal MOSFET: Reliable device for low power analog applications","authors":"Y. Joly, L. Lopez, J. Portal, H. Aziza, P. Masson, J. Ogier, Y. Bert, F. Julien, P. Fornara","doi":"10.1109/ESSDERC.2011.6044176","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044176","url":null,"abstract":"Low power analog circuits needs large and short MOSFETs biased in the sub-threshold area with good performances in terms of matching. In order to reach these specifications, octagonal transistors are proposed. Due to their design, these transistors avoid hump effect. As a consequence, gate-source voltage matching under-threshold is always at its best level. Moreover, the paper shows the device robustness to hot carrier stress is improved on octagonal NMOS; VT matching degradation due to hot carrier stress is also improved with an octagonal design.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116162249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044192
M. Koyama, N. Shigemori, K. Ozawa, K. Tachi, K. Kakushima, O. Nakatsuka, K. Ohmori, K. Tsutsui, A. Nishiyama, N. Sugii, K. Yamada, H. Iwai
Si/Ni-silicide Schottky junctions with atomically flat and thermodynamically stable interfaces have been achieved by using NiSi2 source. The flat interfaces have been obtained from forming thin epitaxial NiSi2 layer without Si substrate consumption on the interfaces. A robust φBn of ∼0.66 eV and ideally stable n-factor of ∼1.00 were achieved from the Schottky barrier diode formed in the straightforward fabrication process. The facts are very beneficial for designing future nano-scale FETs.
利用NiSi2源实现了具有原子平面和热力学稳定界面的Si/ ni -硅化物肖特基结。通过形成薄的外延NiSi2层而无需在界面上消耗Si衬底，可以获得平坦的界面。在简单的制造过程中形成的肖特基势垒二极管获得了稳健的φBn ~ 0.66 eV和理想的稳定n因子~ 1.00。这些事实对未来纳米级场效应管的设计是非常有益的。
{"title":"Si/Ni-Silicide Schottky junctions with atomically flat interfaces using NiSi2 source","authors":"M. Koyama, N. Shigemori, K. Ozawa, K. Tachi, K. Kakushima, O. Nakatsuka, K. Ohmori, K. Tsutsui, A. Nishiyama, N. Sugii, K. Yamada, H. Iwai","doi":"10.1109/ESSDERC.2011.6044192","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044192","url":null,"abstract":"Si/Ni-silicide Schottky junctions with atomically flat and thermodynamically stable interfaces have been achieved by using NiSi2 source. The flat interfaces have been obtained from forming thin epitaxial NiSi2 layer without Si substrate consumption on the interfaces. A robust φBn of ∼0.66 eV and ideally stable n-factor of ∼1.00 were achieved from the Schottky barrier diode formed in the straightforward fabrication process. The facts are very beneficial for designing future nano-scale FETs.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122303666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044230
B. Kim, Y. Ji, Seungmi Lee, B.K. Jeon, Kee-jeung Lee, K. Hong, Sungki Park
The origin of flat band voltage shift phenomena using arsenic ion-implant in High-k/Metal Inserted Poly Si (HK/MIPS) gate stacks was investigated. Arsenic ion-implantations were carried out on HfSiO and HfSiON dielectric layers. Precise arsenic profile was obtained through front and backside SIMS analysis. From the electrical and physical analysis, we verified that the flat band voltage was shifted due to an arsenic dipole formation at high-k/metal interface. The negative shift of 480mV was obtained with the optimized arsenic ion implant condition.
{"title":"The study of flat-band voltage shift using arsenic ion-implantation with High-k/Metal Inserted Poly Si gate stacks","authors":"B. Kim, Y. Ji, Seungmi Lee, B.K. Jeon, Kee-jeung Lee, K. Hong, Sungki Park","doi":"10.1109/ESSDERC.2011.6044230","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044230","url":null,"abstract":"The origin of flat band voltage shift phenomena using arsenic ion-implant in High-k/Metal Inserted Poly Si (HK/MIPS) gate stacks was investigated. Arsenic ion-implantations were carried out on HfSiO and HfSiON dielectric layers. Precise arsenic profile was obtained through front and backside SIMS analysis. From the electrical and physical analysis, we verified that the flat band voltage was shifted due to an arsenic dipole formation at high-k/metal interface. The negative shift of 480mV was obtained with the optimized arsenic ion implant condition.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129246984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044168
M. Kolahdouz, M. Ostling, H. Radamson
SiGe(C)/Si(C) multi quantum wells (MQWs) individually or in series with a Schottky diode (SQW) have been characterized as the thermistor materials for high performance bolometer application. The thermal response of the thermistor materials is expressed in temperature coefficient of resistance (TCR) and an excellent value of 6%/K is obtained for the SQWs. The noise power spectrum density was also measured and the K1/f was estimated as low as 4.7×10−14. The outstanding characteristics for the SQWs are due to low defect density and high interfacial quality in the multilayer structures. These results are very promising for the rising market of low cost IR detectors in the near future.
{"title":"A low cost multi quantum SiGe/Si/Schottky structure for high performance IR detectors","authors":"M. Kolahdouz, M. Ostling, H. Radamson","doi":"10.1109/ESSDERC.2011.6044168","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044168","url":null,"abstract":"SiGe(C)/Si(C) multi quantum wells (MQWs) individually or in series with a Schottky diode (SQW) have been characterized as the thermistor materials for high performance bolometer application. The thermal response of the thermistor materials is expressed in temperature coefficient of resistance (TCR) and an excellent value of 6%/K is obtained for the SQWs. The noise power spectrum density was also measured and the K1/f was estimated as low as 4.7×10−14. The outstanding characteristics for the SQWs are due to low defect density and high interfacial quality in the multilayer structures. These results are very promising for the rising market of low cost IR detectors in the near future.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113956668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044224
C. Cagli, F. Nardi, D. Ielmini, B. Harteneck, Z. Tan, Y. Zhang
For the development of crossbar memory arrays with density approaching one Tb/cm2, bottom-up techniques employing nanowire (NW) synthesis and assembly seem most promising. This work demonstrates a resistive switching memory (RRAM) based on core-shell NWs, with Ni core and NiO shell, where resistive switching takes place in the active NiO shell. RRAM devices with two NWs in a crossbar layout display a resistance window of about 5 decades. Unipolar resistance switching is evidenced to occur in the NiO shell at the cross-point junction between NWs. These results support core-shell NWs with metallic core and metal-oxide shell as promising building blocks for functional/scalable bottom-up RRAM technology.
{"title":"Nanowire-based RRAM crossbar memory with metallic core-oxide shell nanostructure","authors":"C. Cagli, F. Nardi, D. Ielmini, B. Harteneck, Z. Tan, Y. Zhang","doi":"10.1109/ESSDERC.2011.6044224","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044224","url":null,"abstract":"For the development of crossbar memory arrays with density approaching one Tb/cm2, bottom-up techniques employing nanowire (NW) synthesis and assembly seem most promising. This work demonstrates a resistive switching memory (RRAM) based on core-shell NWs, with Ni core and NiO shell, where resistive switching takes place in the active NiO shell. RRAM devices with two NWs in a crossbar layout display a resistance window of about 5 decades. Unipolar resistance switching is evidenced to occur in the NiO shell at the cross-point junction between NWs. These results support core-shell NWs with metallic core and metal-oxide shell as promising building blocks for functional/scalable bottom-up RRAM technology.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128167351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044204
R. Pagano, D. Corso, S. Lombardo, S. Libertino, G. Valvo, D. Sanfilippo, A. Russo, P. Fallica, A. Pappalardo, P. Finocchiaro
This paper reports on the electrical characteristics of silicon photomultipliers (SiPM) with optimized optical trench technology. The SiPM arrays were characterized from single pixels up to the full 64×64 pixel device. The data clearly show a perfect scaling of the dark current with the pixel number, thus indicating an almost ideal insulation among the pixels in the whole voltage operating range.
{"title":"Optimized silicon photomultipliers with optical trenches","authors":"R. Pagano, D. Corso, S. Lombardo, S. Libertino, G. Valvo, D. Sanfilippo, A. Russo, P. Fallica, A. Pappalardo, P. Finocchiaro","doi":"10.1109/ESSDERC.2011.6044204","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044204","url":null,"abstract":"This paper reports on the electrical characteristics of silicon photomultipliers (SiPM) with optimized optical trench technology. The SiPM arrays were characterized from single pixels up to the full 64×64 pixel device. The data clearly show a perfect scaling of the dark current with the pixel number, thus indicating an almost ideal insulation among the pixels in the whole voltage operating range.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"13 19","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133085693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044240
J. Rabaey
The exact functioning and operation of the brain has been and still is to a major degree a great mystery. The recent introduction of advanced imaging tools such as fMRI, EEG and eCoG and, most recently, direct neural sensing are throwing the doors of neuroscience wide open, and enable direct in-vivo observations of the brain at work in dynamic conditions. This may help to address a broad range of neural impairments and diseases, such as stroke, paralysis, epilepsy, depression, etc. However, for all of these to happen it is essential that neural interface circuitry is developed that surpasses the state of the art in ultra-low power miniaturized design by at least an order of magnitude. Furthermore, the resulting sensory/stimulation nodes have to be energy-self contained and support wireless links > 1 Mbps. This paper explores the opportunities of accomplishing just that, and demonstrates the feasibility with a number of examples. The potential outcomes of these developments are just "mind-blowing", and can dramatically impact the evolution of human-cyber interfaces in the decades to come.
{"title":"Brain-machine interfaces as the new frontier in extreme miniaturization","authors":"J. Rabaey","doi":"10.1109/ESSDERC.2011.6044240","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044240","url":null,"abstract":"The exact functioning and operation of the brain has been and still is to a major degree a great mystery. The recent introduction of advanced imaging tools such as fMRI, EEG and eCoG and, most recently, direct neural sensing are throwing the doors of neuroscience wide open, and enable direct in-vivo observations of the brain at work in dynamic conditions. This may help to address a broad range of neural impairments and diseases, such as stroke, paralysis, epilepsy, depression, etc. However, for all of these to happen it is essential that neural interface circuitry is developed that surpasses the state of the art in ultra-low power miniaturized design by at least an order of magnitude. Furthermore, the resulting sensory/stimulation nodes have to be energy-self contained and support wireless links > 1 Mbps. This paper explores the opportunities of accomplishing just that, and demonstrates the feasibility with a number of examples. The potential outcomes of these developments are just \"mind-blowing\", and can dramatically impact the evolution of human-cyber interfaces in the decades to come.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131057785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：