P. McNamara, S. Saxena, C. Guardiani, H. Taguchi, Emiko Yoshida, Naoki Takahashi, Koji Miyamoto, K. Sugawara, Takeshi Matsunaga
{"title":"Design for manufacturability characterization and optimization of mixed-signal IP","authors":"P. McNamara, S. Saxena, C. Guardiani, H. Taguchi, Emiko Yoshida, Naoki Takahashi, Koji Miyamoto, K. Sugawara, Takeshi Matsunaga","doi":"10.1109/CICC.2001.929771","DOIUrl":null,"url":null,"abstract":"This paper presents results of applying a statistically based parametric yield modeling approach to quantify current manufacturing yield and potential yield improvement of mixed-signal blocks. This design for manufacturability methodology is used to statistically characterize and quantify parametric yield optimization of a 2-channel 9-bit DAC manufactured in a 0.4C /spl mu/m CMOS process. Parametric yield loss characterization and optimization are validated in silicon to be 15% and 4%, respectively.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2001.929771","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
This paper presents results of applying a statistically based parametric yield modeling approach to quantify current manufacturing yield and potential yield improvement of mixed-signal blocks. This design for manufacturability methodology is used to statistically characterize and quantify parametric yield optimization of a 2-channel 9-bit DAC manufactured in a 0.4C /spl mu/m CMOS process. Parametric yield loss characterization and optimization are validated in silicon to be 15% and 4%, respectively.
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