{"title":"Upset-like fault injection in VHDL descriptions: A method and preliminary results","authors":"R. Velazco, R. Leveugle, O. Calvo","doi":"10.1109/DFTVS.2001.966778","DOIUrl":null,"url":null,"abstract":"Investigates an approach allowing one to evaluate the consequences of single event upset phenomena for the reliable operation of processors. The method is based on the simulation of bit flips using a modified version of a high-level circuit description. Preliminary results illustrate the potential of this new strategy.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFTVS.2001.966778","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 19
Abstract
Investigates an approach allowing one to evaluate the consequences of single event upset phenomena for the reliable operation of processors. The method is based on the simulation of bit flips using a modified version of a high-level circuit description. Preliminary results illustrate the potential of this new strategy.
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