Transition test generation using replicate-and-reduce transform for scan-based designs

Abstract

In this paper, we presented a new transition ATPG methodology flow for scan-based design using broad-side test format. A replicate and reduce (RR) circuit transform is introduced, which maps the two time frame processing of transition fault ATPG to a single time frame processing on duplicated iterative blocks with reduced connection. A complete ATPG methodology flow is proposed to generate high coverage transition test patterns both fast and efficiently. Experimentation results on several circuits from next generation Motorola microprocessor design are presented to show the effectiveness of our approach.