Hardware implementation issues of cascade filters MUD for multirate WCDMA systems

Q. Ho, D. Massicotte
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引用次数: 2

Abstract

The hardware implementation issues of multiuser interference cancellation techniques for multirate asynchronous direct-sequence code division multi-access (DS-CDMA) systems based on variable spreading factor (VSF) are investigated. Based on an algorithm for monorate systems based on cascade adaptive filter multi-user detector (CF-MUD), an analysis is done to choose the best tradeoffs between hardware implementation and algorithmic performance in the third generation (3G) communication scenarios. We investigate two popular techniques, namely low-rate detector (LRD) and high-rate detector (HRD). The goal aims to extend the CF-MUD algorithm and reuse its FPGA-targeted architectures that we previously developed for multirate systems. The developed architectures can be used as an intellectual property (IP) core in a system on a programmable chip (SOPC) based on Xilinx/sup /spl copy// Virtex II Pro and Virtex II processing MUD function for asynchronous multirate systems.
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多速率WCDMA系统级联滤波器MUD的硬件实现问题
研究了基于可变扩频因子(VSF)的多速率异步直序码分多址(DS-CDMA)系统多用户干扰消除技术的硬件实现问题。基于一种基于级联自适应滤波多用户检测器(CF-MUD)的单系统算法,分析了第三代(3G)通信场景中硬件实现和算法性能之间的最佳权衡。我们研究了两种流行的技术,即低速率检测器(LRD)和高速率检测器(HRD)。我们的目标是扩展CF-MUD算法,并重用我们之前为多速率系统开发的fpga目标架构。所开发的架构可以作为基于Xilinx/sup /spl copy// Virtex II Pro和Virtex II处理MUD功能的可编程芯片(SOPC)系统的知识产权(IP)核心,用于异步多速率系统。
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