{"title":"A 0.5–3.5GHz wideband CMOS LNA for LTE application","authors":"Wei-Rern Liao, Jeng-Rern Yang","doi":"10.1109/IMFEDK.2016.7521677","DOIUrl":null,"url":null,"abstract":"This paper presents a 0.5-3.5GHz wideband CMOS low noise amplifier (LNA) for LTE application. The LNA design is based on a common source (CS) cascade amplifier with resistive feedback that is used to do input matching and reduce the noise figure. Source follower and LC series resonances are used to do output matching. The LNA achieves the gain of 17dB ~ 22dB, a noise figure (NF) of 2.23 ~ 2.68 dB at frequency from 0.5 to 3.5 GHz, The DC power consumption is 32.8mW at 1.8 V supply voltage. The LNA is fabricated with TSMC 0.18-μm CMOS process. The chip size is 0.6mm*0.8mm.","PeriodicalId":293371,"journal":{"name":"2016 IEEE International Meeting for Future of Electron Devices, Kansai (IMFEDK)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Meeting for Future of Electron Devices, Kansai (IMFEDK)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMFEDK.2016.7521677","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
This paper presents a 0.5-3.5GHz wideband CMOS low noise amplifier (LNA) for LTE application. The LNA design is based on a common source (CS) cascade amplifier with resistive feedback that is used to do input matching and reduce the noise figure. Source follower and LC series resonances are used to do output matching. The LNA achieves the gain of 17dB ~ 22dB, a noise figure (NF) of 2.23 ~ 2.68 dB at frequency from 0.5 to 3.5 GHz, The DC power consumption is 32.8mW at 1.8 V supply voltage. The LNA is fabricated with TSMC 0.18-μm CMOS process. The chip size is 0.6mm*0.8mm.
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