Integrated III-V nanoelectronic devices on Si

Abstract

I will give an overview of our recent work on the integration of III-V semiconductor nano-structures on silicon (Si) for electronic devices. The template-assisted selective epitaxy (TASE) used to monolithically integrate high crystal quality III-V nanostructures on Si is introduced. The challenges and recent progress of the development of nanoscale III-V MOSFETs and Tunnel FETs is discussed and a complementary p-type InAs-Si and η-type InAs-GaSb TFET technology is demonstrated.