A /spl mu/Watt postage stamp PC

David G. England
{"title":"A /spl mu/Watt postage stamp PC","authors":"David G. England","doi":"10.1109/ASIC.1998.722819","DOIUrl":null,"url":null,"abstract":"This paper gives details of a Intel386/sup TM/ microprocessor based system in a single package. The functionality of this single device is somewhat equivalent to a 1990 PC. However, the design includes many features that significantly reduce power consumption. The design incorporates 'Few Chip Package (FCP)' technology to marry 0.35 micron logic die and 0.35 micron flash memory technologies in a single 23 mm package. The main feature of the part is its reduced average power consumption of less than 1 mW in target applications.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1998.722819","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

This paper gives details of a Intel386/sup TM/ microprocessor based system in a single package. The functionality of this single device is somewhat equivalent to a 1990 PC. However, the design includes many features that significantly reduce power consumption. The design incorporates 'Few Chip Package (FCP)' technology to marry 0.35 micron logic die and 0.35 micron flash memory technologies in a single 23 mm package. The main feature of the part is its reduced average power consumption of less than 1 mW in target applications.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
A /spl亩/瓦特邮票PC机
本文详细介绍了一个基于Intel386/sup TM/微处理器的单包系统。这个单一设备的功能在某种程度上相当于一台1990年的个人电脑。然而,该设计包含了许多显著降低功耗的功能。该设计采用了“少数芯片封装(FCP)”技术,将0.35微米逻辑芯片和0.35微米闪存技术集成在一个23毫米封装中。该部件的主要特点是其在目标应用中的平均功耗低于1 mW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Relaxed partitioning balance constraints in top-down placement Design and test of a CMOS low-power mixed-analog/digital ASIC for radiation detector readout front ends Substrate noise in mixed signal circuits: two case studies [CMOS] 800 K gates of random logic in four months: discussion on design methodologies based on "IDEFIX" ASIC experience Methodology for process portable hard IP block creation using cell based array architecture
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1